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PDF ML1001 Data sheet ( Hoja de datos )
| Número de pieza | ML1001 | |
| Descripción | Static LCD COG Driver | |
| Fabricantes | Minilogic Device | |
| Logotipo |  |
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ML1001
ML1001 Series Static LCD COG Driver
v Application
v Features
u Instrument LCD Module
u Telephone LCD Module
u Automotive LCD Module
u Handheld Device LCD Module
l AGoldBumpChipwithoutexternalcomponent.
l Logic & LCD power supply: 2.0V to 6.0V
l Typical Current consumption: 25uA at VIN = 3V
& no load condition.
l Number of segments: 40
l Cascade the ML1001 to form a single piece of 80
or 120 segments LCD driver.
l Simple3pinmicrocontrollerinterfacethroughDIN, DCLK
& LOAD.
l Blink of the display data.
l OfferbestcontrastandwidestviewingangleofTNLCD
technology.
l NotemperaturecompensationneededforTopr=-40oC to
80oC.
v General Description
ML1001 static LCD COG (chip on glass) driver is 40 segments LCD driver with gold bump. It can be
cascaded to form a single piece of 80 or 120 segments LCD drivers. It targets at custom TN LCD COG
Module product which requires the best quality of TN LCD technology. With the use of ML1001 series
driver, it offers the best contrast, the widest viewing angle, the widest range of operating voltage and the
widest range of operating temperature when compared to the multiplex method.
Our ML1001 includes an internal 32kHz oscillator, a 40-bit shift register, a 40-bit data register, a 16-bit
segment driver, a 24-bit segment driver, two common drivers, a blink control circuit, a power-up reset
circuit and a frequency divider which offer the necessary clock signals for Blink control, segment &
common driver circuit.
Through the DIN pin, the display data is serially shifted into the 40-bit shift register at the rising edge of
DCLK signal. The display data, which is going to be displayed on the attached LCD, is then stored in the
40-bit data register at the rising edge of the LOAD signal.
Other features like blinking of the display data by the BEN and BCLK, disable the internal oscillator by
the OEN, input an external clock signal to the FIN, and enable or disable the segment and common driver
by the SEN1, SEN2, CEN1A and CEN1B, are included.
v Ordering Information
Part Number
ML1001-1U
ML1001-2U
ML1001-3U
Description
Package Form
a 40 segment static LCD driver Gold Bump Die
a 80 segment static LCD driver Gold Bump Die
a 120 segment static LCD driver Gold Bump Die
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ML1001
ii) Oscillator
a) Internal clock
The internal logic and the LCD driving signal of ML1001 are clocked either by the built-in oscillator or
from an external clock. When the internal oscillator is used, OEN should be connected to GND and the
OOUT should be connected to FIN. The oscillator will oscillate at 32 kHz and the frequency is
independent in the range of 2.0V < VDD < 6.0V .
b) External clock
When using an external clock, the OEN is connected to VDD then connects the external clock to FIN.
iii) Timing
ML1001 have several frequencies of clock signal for the users to choose for the LCD display clock (ie.
LCLK) and the blink clock (ie. BCLK). They include the following clock signals :
Frequency of Clock Signal at FIN = 32 kHz
2 KHz
1 KHz
500 Hz
256 Hz
128 Hz
4 Hz
2 Hz
1 Hz
Actual Divider of FIN
1/16
1/32
1/64
1/128
1/256
1/8192
1/16384
1/32768
Target Input Pin
LCLK
BCLK
iv) Segment outputs
ML1001 has 40 segment outputs which should be connected directly to the LCD. If less than 40 segments
are required, the unused segments should be left open circuit. Users can disable the first 1 to 16 segments
and the last 17 to 40 segments by connecting the SEN1 and SEN2 to VDD, respectively. The segment
outputs shall output GND level after disabling it.
v) Common outputs
ML1001 consists of 2 common signals (ie. COM1A & COM1B). These two common signals are the
inversion of the LCLK. The common outputs should be left open-circuit if the outputs are unused. Users
can disable the COM1A and COM1B by connecting the CEN1A and CEN1B to VDD, respectively. The
common outputs will change to GND after disabling it.
vi) Blink
ML1001 has a blink function that users shall connect the BEN to GND and input the blink clock (ie.
BCLK) either by connecting ML1001 output clock signal from Frequency Divider or an external clock
signal. Users shall disable blink function by connecting BEN to VDD.
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ML1001
ML1001-3U Standard Application
Pin
N1 umber
2
3
4
5
6
Pin Name
VDD
GND
LOAD
DIN
DCLK
CHECK
Note :
Chip 1 Pad Coordinate shall follow “Table of Pad Location”.
Chip 2 Pad Coordinate shall be calculated as follow :
Chip 2 X-Coordinate = Chip 1 X-Coordinate + 3,440um
Chip 2 Y-Coordinate = Chip 1 Y-Coordinate
Chip 3 Pad Coordinate shall be calculated as follow :
Chip 3 X-Coordinate = Chip 1 X-Coordinate + 6,880um
Chip 3 Y-Coordinate = Chip 1 Y-Coordinate
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ML1001.PDF ] | |
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