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PDF CY7C0241AV-20AC Data sheet ( Hoja de datos )
| Número de pieza | CY7C0241AV-20AC | |
| Descripción | 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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25/0251
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16K x 16 organization (CY7C024AV/025AV/026AV)
• 4/8K x 18 organization (CY7C0241AV/0251AV)
• 16K x 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 and 25 ns
• Low operating power
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Master/
Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT70V24, 70V25, and 7V0261.
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CEL
LBL
OEL
[1]
I/O8/9L–I/O15/17L
[2]
I/O0L–I/O7/8L
8/9
8/9
I/O
Control
I/O
Control
CER
LBR
OER
8/9 [1]
I/O8/9L–I/O15/17R
8/9 [2]
I/O0L–I/O7/8R
[3]
A0L–A11/1213L
12/13/14 Address
Decode
True Dual-Ported
RAM Array
[3]
A0L–A11/12/13L
CEL
OEL
R/WL
SEML [4]
BUSYL
INTL
UBL
LBL
12/13/14
Interrupt
Semaphore
Arbitration
M/S
Notes:
1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
2. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
4. BUSY is an output in master mode and an input in slave mode.
Address 12/13/14
Decode
[3]
A0R–A11/12/13R
12/13/14
[3]
A0R–A11/12/13R
CER
OER
R/WR
SEMR
[4]
BUSYR
INTR
UBR
LBR
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06052 Rev. **
Revised September 21, 2001
1 page  
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Definitions
Left Port
CEL
R/WL
OEL
A0L–A13L
I/O0L–I/O17L
SEML
UBL
LBL
INTL
BUSYL
M/S
VCC
GND
NC
Right Port
CER
R/WR
OER
A0R–A13R
I/O0R–I/O17R
SEMR
UBR
LBR
INTR
BUSYR
Description
Chip Enable
Read/Write Enable
Output Enable
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K)
Data Bus Input/Output
Semaphore Enable
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices)
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to VCC+0.5V
DC Input Voltage[9] ..................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Industrial[10]
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 300 mV
3.3V ± 300 mV
Notes:
9. Pulse width < 20 ns.
10. Industrial parts are available in CY7C026AV and CY7C036AV only.
Document #: 38-06052 Rev. **
Page 5 of 19
5 Page 
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[36]
A 0–A 2
SEM
VALID ADRESS
tAW
tSCE
tHA
tSAA
VALID ADRESS
tSOP
tACE
tOHA
I/O 0
R/W
OE
tSD
DATAIN VALID
tSA
tPWE
tHD
DATAOUT VALID
WRITE CYCLE
tSWRD
tSOP
tDOE
READ CYCLE
Timing Diagram of Semaphore Contention[37, 38, 39]
A0L –A2L
MATCH
R/WL
SEM L
A 0R–A2R
R/WR
SEM R
tSPS
MATCH
Notes:
36. CE = HIGH for the duration of the above timing (both write and read cycle).
37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
38. Semaphores are reset (available to both ports) at cycle start.
39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 38-06052 Rev. **
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY7C0241AV-20AC.PDF ] | |
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