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ADV7181B Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7181B
Beschreibung Multiformat SDTV Video Decoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7181B Datasheet, Funktion
Multiformat SDTV Video Decoder
ADV7181B
FEATURES
Multiformat video decoder supports NTSC-(M, J, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™),
signal processing, and enhanced FIFO management
give mini-TBC functionality
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
Chroma transient improvement (CTI)
Digital noise reduction (DNR)
Multiple programmable analog input formats
Composite video (CVBS)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit)
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
Differential phase: 0.6° typ
GENERAL DESCRIPTION
The ADV7181B integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data compatible with 16-bit/8-bit
CCIR601/CCIR656.
The advanced, highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The six analog input channels accept standard composite,
S-Video, and YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively,
these can be bypassed for manual settings.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Programmable video controls
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video output with no I/P)
VBI decode support for
close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
VBI decode support for
close captioning, WSS, CGMS, EDTV, and
Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade: –40°C to +85°C
64-lead LQFP Pb-free package and 64-lead LFCSP package
APPLICATIONS
DVD recorders
PC video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receivers
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line-locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181B modes
are set up over a 2-wire, serial, bidirectional port (I2C-compatible).
The ADV7181B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7181B is available in two packages, a small 64-lead
LQFP Pb-free package and a 64-lead LFCSP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.






ADV7181B Datasheet, Funktion
ADV7181B
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating temperature range, unless
otherwise noted.
Table 1.
Parameter1, 2
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS3
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
Power-Down Current
Power-Up Time
Symbol
N
INL
DNL
VIH
VIL
IIN
CIN
VOH
VOL
ILEAK
COUT
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
IAVDD
IPWRDN
tPWRUP
Test Conditions
BSL at 54 MHz
BSL at 54 MHz
Pin 29
All other pins
ISOURCE = 0.4 mA
ISINK = 3.2 mA
CVBS input4
YPrPb input5
Min Typ
−0.475/+0.6
–0.25/+0.5
2
–50
–10
2.4
1.65 1.8
3.0 3.3
1.65 1.8
3.15 3.3
80
2
10.5
85
180
1.5
20
Max
9
−1.5/+2
–0.7/+2
0.8
+50
+10
10
0.4
10
20
2
3.6
2.0
3.45
Unit
Bits
LSB
LSB
V
V
μA
μA
pF
V
V
μA
pF
V
V
V
V
mA
mA
mA
mA
mA
mA
ms
1Temperature range: TMIN to TMAX, –40°C to +85°C.
2The min/max specifications are guaranteed over this range.
3Guaranteed by characterization.
4ADC1 and ADC2 powered down.
5All three ADCs powered on.
Rev. B | Page 6 of 100

6 Page









ADV7181B pdf, datenblatt
ADV7181B
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Type
3, 10, 24, 34, 57 DGND
G
32, 37, 43, 45 AGND
G
4, 11
DVDDIO
P
23, 58
DVDD
P
40
AVDD
P
31
PVDD
P
35, 36, 46 to 49 AIN1 to AIN6 I
12, 13, 27, 28,
33, 50, 55, 56
NC
5 to 8, 14 to 19, P0 to P15
25, 26, 59 to 62
O
2 HS O
64 VS O
63
FIELD
O
1
INTRQ
O
53 SDA I/O
54
SCLK
I
52
ALSB
I
51
RESET
I
20 LLC O
22
XTAL
I
21
XTAL1
O
29
PWRDN
I
30 ELPF I
9 SFL O
41
42
38, 39
44
REFOUT
O
CML O
CAPY1, CAPY2 I
CAPC2
I
Description
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
No Connect Pins.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in Table 83.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
This pin selects the I2C address for the ADV7181B. ALSB set to a Logic 0 sets the address for a
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7181B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7181B. Nominally 27 MHz,
but varies up or down according to video line length.
This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7181B. In crystal mode, the crystal
must be a fundamental crystal.
A logic low on this pin places the ADV7181B in power-down mode. Refer to the I2C Register
Maps section for more options on power-down modes for the ADV7181B.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 45.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video
encoder.
Internal Voltage Reference Output. Refer to Figure 45 for a recommended capacitor network for
this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to Figure 45 for a
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 45 for a recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 45 for a recommended capacitor network for this pin.
Rev. B | Page 12 of 100

12 Page





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