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PDF COP87L88RWV-XE Data sheet ( Hoja de datos )
| Número de pieza | COP87L88RWV-XE | |
| Descripción | 8-Bit One-Time Programmable OTP Microcontroller with Pulse Train Generators and Capture Modules | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 2000
COP87L88RW
8-Bit One-Time Programmable (OTP) Microcontroller
with Pulse Train Generators and Capture Modules
General Description
The COP87L88RW OTP microcontrollers are large memory
(32k), highly integrated COP8™ Feature core devices, with
advanced features including including Pulse Train Genera-
tors, Capture Modules, and hardware multiply/divide. These
multi-chip CMOS devices are suited for applications requir-
ing a full featured controller with high I/O pincount, pulse
generation and capture, and a full-duplex USART, and for
pre-production devices for ROM designs. Pin and software
compatible 16k ROM versions are available (COP888GW),
along with a range of COP8 software and hardware develop-
ment tools.
Family features include an 8-bit memory mapped architec-
ture, 10MHz CKI with 1µs instruction cycle, hardware
multiply/divide functions, two 100ns capture modules, four
pulse train generators with 16 bit prescalers, two multi-
function 16-bit timer/counters, idle timer, full-duplex USART,
MICROWIRE/PLUS™ serial I/O, two power saving HALT/
IDLE modes, MIWU, high current outputs, software select-
able I/O options, 2.7v-5.5v operation, program code security,
and 68 pin packages.
Devices included in this datasheet are:
Device
COP87L88RW
Memory (bytes)
32k OTP
RAM
(bytes)
512
I/O Pins
64
Packages
68 PLCC
Temperature
-40 to +85˚C
Key Features
n Package: 68 PLCC with I/O pins
n Multiply/divide functions
n Full duplex UART
CPU/Instruction Set Features
n Four pulse train generators with 16-bit prescalersDataSheent41Uµ.csoinmstruction cycle time
n Two 16-bit input capture modules with 8-bit prescalers
n Fourteen multi-source vectored interrupts servicing
n Two 16-bit timers, each with two 16-bit registers
supporting
— Processor independent PWM mode
— External event counter mode
— Input capture mode
n 32 kbytes on-board OTP EPROM with security feature
— External interrupt
— Idle timer T0
— Two timers (each with 2 interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake-Up
— Software trap
— UART (2)
Note: Mask ROMed devices with equivalent on-chip features and pro-
gram memory sizes of 16k is available.
n 512 bytes on-board RAM
— Default VIS
— Capture timers
— Counters (one vector for all four counters)
Additional Peripheral Features
n Idle Timer
n Multi-Input Wake-Up (MIWU) with optional interrupts (8)
n WATCHDOG™ and clock monitor logic
n MICROWIRE/PLUS serial I/O
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) — stack in RAM
n Two 8-bit register indirect data memory pointers
(B and X)
Fully Static CMOS
I/O Features
n Memory mapped I/O
n Software selectable I/O options
— TRI-STATE® output
— Push-pull output
— Weak pull-up input
— High impedance input
n Schmitt trigger inputs on ports G and L
n Two power saving modes: HALT and IDLE
n Single supply operation: 2.7V to 5.5V
n Temperature range: −40˚C to +85˚C
Development Support
n Emulation device for the COP888GW
n Real time emulation and full program debug offered by
MetaLink’s Development System
DataShee
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™, COPS™ microcontrollers, MICROWIRE™, WATCHDOG™ and COP8™ are trademarks of National Semiconductor Corporation.
DataSheet4U.comiceMASTER™ is a trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation DS012855
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AC Electrical Characteristics
−40˚C ≤ TA ≤ 85˚C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
Crystal, Resonator
Ceramic
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 10)
tPD1, tPD0
SO, SK
All Others
MICROWIRE™ Setup Time (tUWS) (Note 8)
MICROWIRE Hold Time (tUWH) (Note 8)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width (Note 9)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2 Input High Time
Timer 1, 2 Input Low Time
Capture Timer High Time
Capture Timer Low Time
Reset Pause Width
Conditions
VCC≥ 4.5V
VCC≥ 4.5V
RL = 2.2k, CL = 100 pF
VCC ≥ 4.5V
VCC ≥ 4.5V
VCC ≥ 4.5V
VCC ≥ 4.5V
VCC ≥ 4.5V
Min Typ Max Units
1.0 DC µs
200 ns
60 ns
0.7 µs
1 µs
20
56 ns
220
1 tc
1
1
1
1 CKI
1 CKI
1 µs
et4U.com
Note 2: Maximum rate of voltage change to be defined.
Note 3: Supply current is measured after running 2000 cydes with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4:
and not
The HALT mode
driving a load; D
will stop CKI from oscillatng. Test
outputs programmed low and not
conditions: All
driving a load.
iDnPpaaurattsmateiSetdehrtoreeVefeCtrCs4,tUoL,H.CcA,oLETm, Fm,oadned
G port I/O’s configured as
entered via setting bit 7 of
outputs and programmed low
the G Port data register. Part
will pull up CKI during HALT in crystal clock mode.
Note 5: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into
programming mode.
Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have sink current
to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC.) The effective resistance to VCC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the
pins. This warning excludes ESD transients.
Note 7: Condition and parameter valid only for part in HALT mode.
Note 8: Parameter characterized but not tested.
Note 9: tc = Instruction Cycle Time
Note 10: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
DataShee
DataSheet4U.com
DS012855-3
FIGURE 3. MICROWIRE/PLUS Timing
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Timers (Continued)
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Figure 8 shows a block diagram of the timer in PWM mode.
The underfIows can be programmed to toggle the TxA output
pin. The underfIows can also be programmed to generate in-
terrupts.
UnderfIows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending fIags under software control. Two control ena-
bIe fIags, TxENA and TxENB, alIow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA wilI cause an interrupt when a timer un-
derflow causes the RxA register to be reloaded into the timer.
Setting the timer enable flag TxENB will cause an interrupt
when a timer underflow causes the RxB register to be re-
loaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Either or both of the timer underflow interrupts may be en-
abled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
Mode 2. ExternaI Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, Tx, is cIocked by the input signal from the TxA pin. The
Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to
be clocked either on a positive or negative edge from the
TxA pin. Underflows from the timer are Iatched into the
TxPNDA pending flag. Setting the TxENA control flag will
cause an interrupt when the timer underflows.
et4U.com
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FIGURE 8. Timer in PWM Mode
DS012855-8
DataShee
DS012855-9
FIGURE 9. Timer in External Event Counter Mode
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB con-
trol flag is set. The occurrence of a positive edge on the TxB
input pin is latched into the TxPNDB flag.
DataSheet4U.com
Figure 9 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being
used as the counter input clock.
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