L9348-DIE1 Datasheet PDF - STMicroelectronics
| Part Number | L9348-DIE1 | |
| Description | QUAD LOW SIDE DRIVER | |
| Manufacturers | STMicroelectronics | |
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L9348
QUAD LOW SIDE DRIVER
s SUPPLY VOLTAGE RANGE: 4.8 TO 18V
s OUTPUT VOLTAGE UP TO 40V
s OUTPUT VOLTAGE CLAMP DURING
RECIRCULATION OF INDUCTIVE LOADS
s OUTPUT CURRENT CAPABILITY 2 X 5A AND
2 X 3A
s LOW POWER DISSIPATION DURING
RECIRCULATION OF INDUCTIVE LOADS BY
INTEGRATED FREE WHEELING DIODES
(3A-DRIVERS ONLY)
s LOW ON-RESISTANCE 2 X 0.2Ω , 2 X 0.35Ω (TYP.)
s OUTPUT SHORT CIRCUIT CURRENT
PROTECTION
s REAL TIME DIAGNOSTIC FUNCTIONS
s OVERTEMPERATURE SHUTDOWN
s SIGNAL- AND POWER-GROUND-LOSS
SHUTDOWN
PowerSO-36
BARE DIE
ORDERING NUMBERS:
L9348
L9348-DIE1
s 3.3V CMOS COMPATIBLE INPUTS AND
STATUS
DESCRIPTION
The L9348 is a monolithic integrated quad low side
driver realized in advanced Multipower-BCD technol-
ogy. It is intended to drive inductive loads (relays,
electromagnetic valves) in automotive and industrial
applications.
Figure 1. Block Diagram
VS
VS Voltage Regulator
+
VREG
–
VDD
VCC
=
IN1
ST1
IN2
ST2
ENA
C 166kHz
VDD
EN
FAIL
OL
VREG
SCP
TSD
GL
VS
≥1
Q1
EN
PGND1
PWRES
C 166kHz
PWRES
EN
EN
VDD
PWRES
PWRES
CHANNEL1
CHANNEL2
Q2
PGND2
VS
C 166kHz
5A - DRIVER
IN3
ST3
IN4
ST4
99AT0073
March 2002
C 166kHz
VDD
EN
VREG
PWRES
C 166kHz
PWRES
FAIL
OL
TSD
FB
EN
SCP
GL
GND
VS
≥1
D3
Q3
EN
PGND3
CHANNEL3
CHANNEL4
D4
Q4
PGND4
3A - DRIVER
1/13
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L9348
Table 5. Electrical Characteristcs
The electrical characteristics are valid within the operating range (Table 4), unless otherwise specified
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
IQlk Output leakage current
VENA = L,Tj = 25°C
1 µA
Tj = 125°C
5 µA
VFD3/4 Forward voltage of
free wheeling diodes D3, D4
ID3/4 = -1.5A
0.5
1.75
V
RPD0 Gate pull down resistor for
nonsupplied VS
VS = 0V,
VD3/4 ≥ 6.5V
0.3 3 kΩ
Timings
tON Output ON delay time
IQ = 1A 1)
0 5 20 µs
tf Output ON fall time
IQ = 1A 1)
0.5 1.5 8 µs
tOFF Output OFF delay time
IQ = 1A 1)
0 10 30 µs
tr Output OFF rise time
IQ = 1A 1)
0.5 1.5 5 µs
tDSO Overload switch-OFF delay time
6 30 65 µs
tD Output OFF status delay time
0.75 1.5 2.25 ms
tfilter error detection filter time
2)
5.8 35 µs
tOLOFF OLOFF error detection filter time
20 70 µs
Digital Inputs (IN1 to IN4, ENA)
VIL Input low voltage
-1.5 1 V
VIH Input high voltage
2 6V
VIHy Input voltage hysteresis
2)
50 100
mV
IIN Input pull down current
VIN = 5V, VS ≥ 6.5V
8 20 40 µA
Digital Outputs (ST1 to ST4)
VSTL Status output voltage in low state IST ≤ 40µA
5)
0 0.4 V
VSTH
Status output voltage in high state IST ≥ -40µA
5)
IST ≥ -120µA
2.5
3.45
V
2
3.45
V
RDIAGL ROUT + RDSON in low state
0.3 0.64 1.5
kΩ
RDIAGH ROUT + RDSON in high state
1.5 3.2
7
(1).See chapter 2.0 Timing Diagrams; resistive load condition; VS ≥ 9V
(2).This parameter will not be tested but assured by design
(3).Wafer-measurement
(4).Measured on P-SO36 devices
(5).Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
kΩ
5/13
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