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L9347 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer L9347
Beschreibung INTELLIGENT QUAD 2X5A/2X2.5A LOW-SIDE SWITCH
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 21 Seiten
L9347 Datasheet, Funktion
L9347
INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH
s Quad low-side switch
s 2 x 5A designed as conventional switch
s 2 x 2.5A designed as switched current-regulator
s Low ON-resistance 2 x 0.2, 2 x 0.35(typ.)
s Power SO-36 - package with integrated
cooling area
s Integrated free-wheeling and clamping Z-diodes
s Output slope control
s Short circuit protection
s Selective overtemperature shutdown
s Open load detection
s Ground and supply loss detection
s External clock control
s Recirculation control
s Regulator drift detection
s Regulator error control
s Regulator resolution 5mA
s Status monitoring
s Status push-pull stages
s Electrostatic discharge (ESD) protection
Figure 1. Pin Connection
PowerSO-36
BARE DIE
ORDERING NUMBERS:
L9347PD
L9347DIE1
DESCRIPTION
The L9347 is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are current
regulators with current range from 250mA to 2.25A
and an accuracy of 10%.
All channels are protected against fail functions.
They are monitored by a status output.
June 2002
99AT0060
GND
PGND3
PGND3
Q3
Q3
D3
D3
Q1
Q1
Q2
Q2
D4
D4
Q4
Q4
PGND4
PGND4
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 CLK
35 ST3
34 IN1
33 IN3
32 ST1
31 PGND1
30 PGND1
29 VS
28 PGND2
27 PGND2
26 TEST
25 EN
24 ST2
23 IN4
22 IN2
21 ST4
20 VDD
19 VCC
1/21






L9347 Datasheet, Funktion
L9347
ELECTRICAL CHARACTERISTCS: (continued)
(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min. Typ.
Additional Diagnostic Functions channel 3 and channel 4 (regulated channels)
DCOUT Output duty cycle range
IQO3,4 Overload current
channel 3,4
filtered with 10ms
VS 6.5V
10
2.5 5
Vrerr Recirculation error shutdown
threshold (open D3/D4)
Iout > 50mA
45 50
PWMdOU Output PWM ratio during drift
T comparison
VIN3 = VIN4 = PWMIN
VTEST = H
-14.3
Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
VIL Input low voltage
-0.3
VIH Input high voltage
2
VIHy Input voltage hysteresis (1)
20
II Input pull down current
VIN = 5V, VS 6.5V
8 20
Digital Outputs (ST1 to ST4)
VSTL Status output voltage in low state (2) IST 40µA
0
VSTH Status output voltage in high state 2)
IST -40µA
IST -120µA
2.5
2
RDIAGL ROUT + RDSON in low state
0.3 0.64
RDIAGH ROUT + RDSON in high state
1.5 3.2
Power Outputs (Q1 to Q4)
RDSON1,2 Static drain-source ON-resistance
Q1 and Q2
(non-reg. channels)
RDSON3,4 Static drain-source ON-resistance
Q3 and Q4
(reg. channels)
IQ = 1A; VS 9.5V
Tj = 25°C
Tj = 125°C(3)
Tj = 150°C(4)
IQ = 1A; VS 9.5V
Tj = 25°C
Tj = 125°C 3)
Tj = 150°C 4)
0.2
0.35
VF_250mA Forward voltage of free wheeling path ID3/4 = -250mA
D3, D4 @250mA
0.5
VF_2.25A Forward voltage of free wheeling path ID3/4 = -2.25A
D3, D4 @2.25A
2.0
Rsens Sense resistor = (VF_2.25A-VF_250mA)/
2A
1
Max.
90
8
60
+14.3
1
6
500
40
0.4
3.45
3.45
1.5
7.0
0.5
0.5
0.75
0.75
1.5
4.5
Unit
%
A
V
%
V
V
mV
µA
V
V
V
k
k
V
V
6/21

6 Page









L9347 pdf, datenblatt
L9347
Diagnostic Table
The status follows the input signal in normal operating conditions.
If any error is detected the status is inverted.
Operating Condition
Normal function
Open load or short to ground
Overload or short to supply
Latched overload
Reset latch
Reset latch
Overtemperature
Latched overtemperature
Reset latch
Reset latch
Recirculation error (reg.chn.)
Latched error
Reset latch
Reset latch
Clock failure (clock loss) (1)
Drift
Failure
No failure
(2)
Test
Input
TEST
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
Enable
Input
ENA
L
L
H
H
L
L
H
H
H
H
H –> L
H
H
H
H –> L
H
H
H
H –> L
H
L
L
H
H
L
L
H
H
Control Input
non-reg./reg.
IN
L
H/PWM
L
H/PWM
L
H/PWM
L
H/PWM
H/PWM
H/PWM
X
H/PWM –> L
H/PWM
H/PWM
X
H/PWM –> L
PWM
PWM
X
PWM –> L
L
H/PWM
L
H/PWM
L
H/PWM
H/PWM
H/PWM
Power Output/
Current reg.
Q
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
(1) during power on sequence only detected on channel 3 and 4 (see description).
(2) This input combination is also used for an internal chip-test and must not be used.
Status
Output
ST
L
L
L
H
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
X
X
L
H
12/21

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