W632GG6KB Datasheet PDF - Winbond
| Part Number | W632GG6KB | |
| Description | 16M x 8-BANKS x 16-BIT DDR3 SDRAM | |
| Manufacturers | Winbond | |
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W632GG6KB
16M 8 BANKS 16 BIT DDR3 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES ...........................................................................................................................................5
3. ORDER INFORMATION .......................................................................................................................6
4. KEY PARAMETERS .............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................8
6. BALL DESCRIPTION............................................................................................................................9
7. BLOCK DIAGRAM ..............................................................................................................................11
8. FUNCTIONAL DESCRIPTION............................................................................................................12
8.1 Basic Functionality ..............................................................................................................................12
8.2 RESET and Initialization Procedure ....................................................................................................12
8.2.1
Power-up Initialization Sequence .....................................................................................12
8.2.2
Reset Initialization with Stable Power ..............................................................................14
8.3 Programming the Mode Registers.......................................................................................................15
8.3.1
Mode Register MR0 .........................................................................................................17
8.3.1.1
Burst Length, Type and Order ................................................................................18
8.3.1.2
CAS Latency...........................................................................................................18
8.3.1.3
Test Mode...............................................................................................................19
8.3.1.4
DLL Reset...............................................................................................................19
8.3.1.5
Write Recovery .......................................................................................................19
8.3.1.6
Precharge PD DLL .................................................................................................19
8.3.2
Mode Register MR1 .........................................................................................................20
8.3.2.1
DLL Enable/Disable................................................................................................20
8.3.2.2
Output Driver Impedance Control ...........................................................................21
8.3.2.3
ODT RTT Values ....................................................................................................21
8.3.2.4
Additive Latency (AL) .............................................................................................21
8.3.2.5
Write leveling ..........................................................................................................21
8.3.2.6
Output Disable........................................................................................................21
8.3.3
Mode Register MR2 .........................................................................................................22
8.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................23
8.3.3.2
CAS Write Latency (CWL) ......................................................................................23
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................23
8.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................23
8.3.4
Mode Register MR3 .........................................................................................................24
8.3.4.1
Multi Purpose Register (MPR) ................................................................................24
8.4 No OPeration (NOP) Command..........................................................................................................25
8.5 Deselect Command.............................................................................................................................25
8.6 DLL-off Mode ......................................................................................................................................25
8.7 DLL on/off switching procedure...........................................................................................................26
8.7.1
DLL “on” to DLL “off” Procedure ..........................................................................26
8.7.2
DLL “off” to DLL “on” Procedure ..........................................................................27
8.8 Input clock frequency change..............................................................................................................28
8.8.1
Frequency change during Self-Refresh............................................................................28
8.8.2
Frequency change during Precharge Power-down ..........................................................28
8.9 Write Leveling .....................................................................................................................................30
Publication Release Date: Dec. 08, 2014
Revision: A04
-1-
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W632GG6KB
1. GENERAL DESCRIPTION
The W632GG6KB is a 2G bits DDR3 SDRAM, organized as 16,777,216 words 8 banks 16 bits.
This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. The W632GG6KB is sorted into the following speed grades: -11, -12, 12I, -15 and 15I.
The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification. The -12 and 12I speed
grades are compliant to the DDR3-1600 (11-11-11) specification (the 12I industrial grade which is
guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -15 and 15I speed grades are compliant to the
DDR3-1333 (9-9-9) specification (the 15I industrial grade which is guaranteed to support -40°C ≤
TCASE ≤ 95°C).
The W632GG6KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Data masks (DM) for write data
Programmable CAS Write Latency (CWL) per operating frequency
Write Latency WL = AL + CWL
Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
Publication Release Date: Dec. 08, 2014
Revision: A04
-5-
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ W632GG6KB.PDF Datasheet ] | |
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