Datenblatt-pdf.com


R8C3JA Schematic ( PDF Datasheet ) - Renesas

Teilenummer R8C3JA
Beschreibung MCU
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R8C3JA Datasheet, Funktion
R8C/3JA Group
RENESAS MCU
REJ03B0263-0110
Rev.1.10
Sep 30, 2009
1. Overview
1.1 Features
The R8C/3JA Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/3JA Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009
Page 1 of 54






R8C3JA Datasheet, Funktion
R8C/3JA Group
1. Overview
1.4 Pin Assignment
Figure 1.3 shows the Pin Assignment (Top View). Tables 1.4 and 1.5 outlines the Pin Name Information by Pin
Number.
P1_0/AN8/LVCMP1/KI0(/TRCIOD)
P0_7/AN0/DA1(/TRCIOC)
P0_6/AN1/DA0(/TRCIOD)
P0_4/AN3/TREO(/TRCIOB)
P0_3/AN4(/CLK1/TRCIOB)
P0_2/AN5(/RXD1/TRCIOA/TRCTRG)
P0_1/AN6(/TXD1/TRCIOA/TRCTRG)
P4_2/VREF
MODE
27 26 25 24 23 22 21 20 19
28 18
29 17
30 16
31 R8C/3JA Group 15
32 14
PWQN0036KA-B(36PJW-B)
33
(top view)
13
34 12
35 11
36 10
123456789
P3_1(/TRBO)
P2_0(/INT1/TRCIOB/TRDIOA0/TRDCLK)
P2_1(/TRCIOC/TRDIOC0)
P2_2(/TRCIOD/TRDIOB0)
P2_3(/TRDIOD0)
P2_4(/TRDIOA1)
P2_5(/TRDIOB1)
P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)
P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC/TRDIOC1/SDA)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3 Pin Assignment (Top View)
REJ03B0263-0110 Rev.1.10 Sep 30, 2009
Page 6 of 54

6 Page









R8C3JA pdf, datenblatt
R8C/3JA Group
2. Central Processing Unit (CPU)
2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009
Page 12 of 54

12 Page





SeitenGesamt 30 Seiten
PDF Download[ R8C3JA Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
R8C3JAMCURenesas
Renesas

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche