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RJF0613JSP Schematic ( PDF Datasheet ) - Renesas

Teilenummer RJF0613JSP
Beschreibung Silicon N Channel MOS FET
Hersteller Renesas
Logo Renesas Logo 




Gesamt 8 Seiten
RJF0613JSP Datasheet, Funktion
Target Specifications Datasheet
RJF0613JSP
60 V - 10 A - N Channel MOS FET
Power Switching
R07DS0874EJ0100
Rev.1.00
Aug 29, 2012
Description
This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in
over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of
high junction temperature like applying over power consumption, over current etc..
Features
Logic level operation (4 V Gate drive).
Built-in the over temperature shut-down circuit.
High endurance capability against to the short circuit.
Latch type shut down operation (need 0 voltage recovery).
Built-in the current limitation circuit.
High density mounting
Power supply voltage applies 12 V and 24 V.
AEC-Q101 Compliant
Outline
RENESAS Package code: PRSP0008DD-D
(Package name: SOP-8 <FP-8DAV> )
8765
1234
G
Gate resistor
Temperature
Sensing
Circuit
Latch
Circuit
Gate
Shut-down
Circuit
Current
Limitation
Circuit
DDDD
1, 2, 3 Source
4 Gate
5, 6, 7, 8 Drain
SSS
Absolute Maximum Ratings
Item
Symbol
Ratings
Drain to source voltage
VDSS
60
Gate to source voltage
Gate to source voltage
Drain current
VGSS
VGSS
ID Note3
16
–2.5
10
Body-drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
IDR
IAP Note 2
EAR Note 2
Pch Note 1
10
4.7
94.7
2.5
Channel temperature
Tch 150
Storage temperature
Tstg –55 to +150
Notes: 1. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW 10s
2. Tch = 25C, Rg 50
3. It provides by the current limitation lower bound value.
(Ta = 25°C)
Unit
V
V
V
A
A
A
mJ
W
C
C
R07DS0874EJ0100 Rev.1.00
Aug 29, 2012
Page 1 of 7






RJF0613JSP Datasheet, Funktion
RJF0613JSP
Switching Time Test Circuit
Vin Monitor
D.U.T.
Vout
Monitor
RL
Vin
10 V
50 Ω
VDD
= 30 V
Target Specifications
Waveform
Vin
Vout
10%
10%
td(on)
90%
tr
90%
90%
td(off)
10%
tf
Vin
10 V
Avalanche Test Circuit
VDS
Monitor
Rg
L
IAP
Monitor
D. U. T
VDD
50 Ω
Avalanche Waveform
EAR = 1 L IAP2
2
V(BR)DSS
V(BR)DSS VDD
V(BR)DSS
IAP
ID VDS
VDD
0
R07DS0874EJ0100 Rev.1.00
Aug 29, 2012
Page 6 of 7

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