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UPD70F3829 Schematic ( PDF Datasheet ) - Renesas

Teilenummer UPD70F3829
Beschreibung 32-bit single-chip microcontrollers
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
UPD70F3829 Datasheet, Funktion
Preliminary Datasheet
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831,
70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
R01DS0029EJ0001
Rev.0.01
V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-ERENESAS MCU
Sep 30, 2010
Description
The μPD70F3826, 70F3827, 70F3828, 70F3829 (V850ES/JF3-E), and μPD70F3830, 70F3831, 70F3832, 70F3833
(V850ES/JF3-E), and μPD70F3834, 70F3835, 70F3836, 70F3837 (V850ES/JG3-E) are products of the V850 32-bit
single-chip microcontrollers, and include peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an
A/D converter, a DMA controller , a CAN controller , a USB function controller , and a Ethernet controller.
In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/JE3-E,
V850ES/JF3-E, and V850ES/JG3-E include instructions executed via a hardware multiplier, saturation instructions, and
bit manipulation instructions.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E Hardware User’s Manual: To be prepared
V850ES Architecture User’s Manual:
U15943E
Features
{ Number of instructions: 83
{ Minimum instruction execution time:
20 ns (@ 50 MHz operation with main clock (fXX))
{ Clock
Main clock oscillation: fX = 3 to 6.25 MHz
Subclock oscillation: fXT = 32.768 kHz
Internal oscillation: fR = 220 kHz (TYP.)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set:
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
{ Memory space:
64 MB linear address space
{ Internal memory
Flash memory: 64/128/256 KB
RAM:
32/48/64 KB
(Including 16 KB of data RAM area)
{ I/O lines Total: 26/42/62
{ Interrupts and exceptions
Non-maskable interrupts: 2 sources
Maskable interrupts: 63/78/85 sources
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
{ Timer/counters
16-bit timer/event counter AA (TAA): 5 channels
16-bit timer/event counter AB (TAB): 1 channel
Motor control function supported
16-bit interval timer M (TMM):
4 channels
16-bit encoder timer T (TMT):
1 channel
{ Real-time counter: 1 channel
{ Watchdog timer: 1 channel
{ Real-time output function: 6 channels
{ A/D converter: 10-bit resolution × 10/10 channels
{ Ethernet controller:
1 channel
{ USB function controller:
1 channel
{ Serial interface
CAN :1 channel (μPD70F3829, 70F3833, 70F3837 only)
Asynchronous serial interface C(UARTC): 3/4 channels
Clocked serial interface F(CSIF):
2/3/5 channels
I2C bus interface:
{ DMA controller: 4 channels
{ Power save function:
2/3 channels
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
{ On-chip debug function
{ Package: 64-pin LQFP (V850ES/JE3-E)
64-pin WQFN (V850ES/JE3-E)
80-pin LQFP (V850ES/JF3-E)
100-pin LQFP (V850ES/JG3-E)
113-pin FBGA (Under planing)
{ Operating supply voltage: 2.85 to 3.6 V
Page 1 of 75






UPD70F3829 Datasheet, Funktion
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
PIN CONFIGURATION
V850ES/JE3-E
64-pin plastic LQFP (fine pitch) (10 × 10)
μPD70F3826GB-GAH-AX
μPD70F3827GB-GAH-AX
μPD70F3828GB-GAH-AX
μPD70F3829GB-GAH-AX
AVREF0
AVSS
P02/NMI
P20/INTP01
VDD
REGCNote2
VSS
X1
X2
RESET
XT1
XT2
P30/TXDC0/SIF2/TIAA00/TOA00
P31/RXDC0/SOF2/TIAA01/TOAA01
P32/ASCKC0/SCKF2/TIAA10/TOAA10
P50/INTP07/DDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48 P1MDIO
47 P1MDC
46 P1COL
45 P1CRS
44 EVDD
43 VSS
42 FLMD0Note1
41 REGCNote2
40 VDD
39 P1RXCLK
38 P1RXER
37 P1RXDV
36 P1RXD3
35 P1RXD2
34 P1RXD1
33 P1RXD0
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7 μF (preliminary value) capacitor.
3. μ PD70F3829 only.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 6 of 75

6 Page









UPD70F3829 pdf, datenblatt
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
V850ES/JF3-E
TIMER / COUNTER FUNCTION
TIAB10 to TIAB13,
EVTAB1,
TRGAB1,
TOAB1OFF
TOAB10 to TOAB13
TOAB1T1 to TOAB1T3,
TOAB1B1 to TOAB1B3
TIAA00, TIAA10, TIAA30, TIAA40,
TIAA01, TIAA21, TIAA31,
TOAA1OFF
TOAA00, TOAA10, TOAA30, TOAA40,
TOAA01, TOAA21, TOAA31,
16-bit
timer/event
counter AB
: 1 ch
16-bit
timer/event
counter AA
: 5 ch
TECR0, TENC00, TENC01,
EVTT0, TIT00, TIT01
TOT00, TOT01
16-bit
interval timer M
: 4 ch
16-bit
timer/counter T
: 1 ch
WDT
RTC
RTP00 to RTP05
RTO
SERIAL INTERFACE FUNCTION
RXDC0 to RXDC3
TXDC0 to TXDC3
ASCKC0
SIF0 to SIF2
SOF0 to SOF2
SCKF0 to SCKF2
SDA00 to SDA02
SCL00 to SCL02
CRXD0
CTXD0
UARTC
: 4 ch
CSIF
: 3 ch
IIC0
: 3 ch
CANNote 3
: 1 ch
Notes 1. μPD70F3830:
μPD70F3831:
μPD70F3832, 70F3833:
2. μPD70F3830:
μPD70F3831:
μPD70F3832, 70F3833:
3. μPD70F3833 only.
ROM
Note1
RAM
Note2
DMA
CPU
Multiplier
16 × 16 32
ALU
PC
32-bit
barrel shifter
System
registers
General-purpose
registers 32 bits × 32
BCU
Ethernet
controller
USB
function
Ports
A/D
converter
CLKOUT
PLL X1
X2
CG XT1
XT2
RESET
INTERRUPT FUNCTION
INTC
Key interrupt
function
NMI
INTP01,
INTP03 to INTP19
KR0 to KR7
DEBUG FUNCTION
DRST
DMS
DCU
DDI
DCK
DDO
Flash
controller
FLMD0
FLMD1
Regulator
EVDD
UVDD
VSS
VDD
REGC
64 KB
128 KB
256 KB
32 KB (Including 16 KB of data RAM)
48 KB (Including 16 KB of data RAM)
64 KB (Including 16 KB of data RAM)
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 12 of 75

12 Page





SeitenGesamt 30 Seiten
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