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M95160-A145 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer M95160-A145
Beschreibung Automotive 16-Kbit serial SPI bus EEPROMs
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
M95160-A145 Datasheet, Funktion
M95160-A125
M95160-A145
Automotive 16-Kbit serial SPI bus EEPROMs
with high-speed clock
Datasheet - production data
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
WFDFPN8 (MF)
2 x 3 mm
Features
Compatible with the Serial Peripheral Interface
(SPI) bus
Memory array
– 16 Kbit (2 Kbyte) of EEPROM
– Page size: 32 byte
– Write protection by block: 1/4, 1/2 or whole
memory
– Additional Write lockable Page
(Identification page)
Extended temperature and voltage ranges
– Up to 125 °C (VCC from 1.7 V to 5.5 V)
– Up to 145 °C (VCC from 2.5 V to 5.5 V)
High speed clock frequency
– 20 MHz for VCC 4.5 V
– 10 MHz for VCC 2.5 V
– 5 MHz for VCC 1.7 V
Schmitt trigger inputs for noise filtering
Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
– 400 k Write cycles at 145 °C
Data retention
– 50 years at 125 °C
– 100 years at 25 °C
ESD Protection (Human Body Model)
– 4000 V
Packages
– RoHS-compliant and halogen-free
(ECOPACK2®)
February 2016
This is information on a product in full production.
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M95160-A145 Datasheet, Funktion
Description
1 Description
M95160-A125 M95160-A145
The M95160-A125 and M95160-A145 are 16-Kbit serial EEPROM Automotive grade
devices operating up to 145°C. They are compliant with the very high level of reliability
defined by the Automotive standard AEC-Q100 grade 0.
The devices are accessed by a simple serial SPI compatible interface running up to
20 MHz.
The memory array is based on advanced true EEPROM technology (Electrically Erasable
PROgrammable Memory). The M95160-A125 and M95160-A145 are byte-alterable
memories (2048 × 8 bits) organized as 64 pages of 32 byte in which the data integrity is
significantly improved with an embedded Error Correction Code logic.
The M95160-A125 and M95160-A145 offer an additional Identification Page (32 byte) in
which the ST device identification can be read. This page can also be used to store
sensitive application parameters which can be later permanently locked in read-only mode.
Figure 1. Logic diagram
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M95160-A145 pdf, datenblatt
Operating features
M95160-A125 M95160-A145
3.4.2
Status Register and data protection
The Status Register format is shown in Table 2 and the status and control bits of the Status
Register are as follows:
Table 2. Status Register format
b7
b6 b5 b4
b3
b2
b1
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Note:
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
Bits b6, b5, b4 are always read as 0.
WIP bit
The WIP bit (Write In Progress) is a read-only flag that indicates the Ready/Busy state of the
device. When a Write command (WRITE, WRSR, WRID, LID) has been decoded and a
Write cycle (tW) is in progress, the device is busy and the WIP bit is set to 1. When WIP=0,
the device is ready to decode a new command.
During a Write cycle, reading continuously the WIP bit allows to detect when the device
becomes ready (WIP=0) to decode a new command.
WEL bit
The WEL bit (Write Enable Latch) bit is a flag that indicates the status of the internal Write
Enable Latch. When WEL is set to 1, the Write instructions (WRITE, WRSR, WRID, LID) are
executed; when WEL is set to 0, any decoded Write instruction is not executed.
The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the
following events:
Write Disable (WRDI) instruction completion
Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle
time tW
Power-up
BP1, BP0 bits
The Block Protect bits (BP1, BP0) are non-volatile. BP1,BP0 bits define the size of the
memory block to be protected against write instructions, as defined in Table 2. These bits
are written with the Write Status Register (WRSR) instruction, provided that the Status
Register is not protected (refer to “SRWD bit and W input signal”, on page 13).
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