Datenblatt-pdf.com


M93S46-125 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer M93S46-125
Beschreibung MICROWIRE serial EEPROM
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 28 Seiten
M93S46-125 Datasheet, Funktion
M93S66-125 M93S56-125
M93S46-125
Automotive 4-Kbit, 2-Kbit and 1-Kbit
MICROWIRE serial EEPROM with block protection
Datasheet production data
Features
Industry standard MICROWIRETM bus
Single supply voltage: 2.5 to 5.5 V
Single organization: by word (x16)
Programming instructions that work on: word or
entire memory
Self-timed programming cycle with auto-erase
User-defined write-protected area
Page Write mode (4 words)
Ready/Busy signal during programming
Speed: 2-MHz clock rate, 5 ms write time
Sequential Read operation
Enhanced ESD/Latch-up behavior
More than 1 million Erase/Write cycles
More than 40-year data retention
SO8 (MN)
150 mil width
March 2012
This is information on a product in full production.
Doc ID 022567 Rev 1
1/28
www.st.com
1






M93S46-125 Datasheet, Funktion
Description
M93S66-125 M93S56-125 M93S46-125
Chip Select Input (S) is held High, the M93Sx6-125 can output a sequential stream of data
words. In this way, the memory can be read as a data stream from 16 to 4096 bits (for the
M93S66-125), or continuously as the address counter automatically rolls over to 00h when
the highest address is reached.
Within the time required by a programming cycle (tW), up to 4 words may be written with
help of the Page Write instruction. the whole memory may also be erased, or set to a
predetermined pattern, by using the Write All instruction.
Within the memory, a user defined area may be protected against further Write instructions.
The size of this area is defined by the content of a Protection register, located outside of the
memory array. As a final protection step, data may be permanently protected by
programming a One Time Programming (OTP) bit which locks the Protection register
content.
Programming is internally self-timed (the external clock signal on Serial Clock (C) may be
stopped or left running after the start of a Write cycle) and does not require an erase cycle
prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the
word locations of the M93Sx6-125, the Page Write instruction writes up to 4 words of 16 bits
to sequential locations, assuming in both cases that all addresses are outside the Write
protected area. After the start of the programming cycle, a Busy/Ready signal is available on
Serial Data Output (Q) when Chip Select Input (S) is driven High.
An internal Power-on Data Protection mechanism in the M93Sx6-125 inhibits the device
when the supply is too low.
Figure 2. 8-pin package connections (top view)
Note:
See Section 9: Package mechanical data section for package dimensions, and how to
identify pin-1.
6/28 Doc ID 022567 Rev 1

6 Page









M93S46-125 pdf, datenblatt
Instructions
M93S66-125 M93S56-125 M93S46-125
Figure 4. PAWRITE and WRAL sequence
PAGE
WRITE
PRE
W
S
D 1 1 1 An A0 Dn
CHECK
STATUS
D0
Q
ADDR
OP
CODE
DATA IN
BUSY
READY
3.4
WRITE
ALL
PRE
W
S
D 1 0 0 0 1 Xn X0 Dn
CHECK
STATUS
D0
Q
ADDR
OP
CODE
DATA IN
BUSY
1. For the meanings of An, Xn and Dn, please see Table 2 and Table 3.
READY
AI00890C
Page Write
A Page Write to Memory (PAWRITE) instruction contains the first address to be written,
followed by up to 4 data words.
After the receipt of each data word, bits A1-A0 of the internal address register are
incremented, the high order bits remaining unchanged (A7-A2 for M93S66-125, M93S56-
125; A5-A2 for M93S46-125). Users must take care, in the software, to ensure that the last
word address has the same upper order address bits as the initial address transmitted to
avoid address roll-over.
The Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words
addresses the protected area.
Write Enable (W) must be held High before and during the instruction. Input address and
data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or
12/28
Doc ID 022567 Rev 1

12 Page





SeitenGesamt 28 Seiten
PDF Download[ M93S46-125 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
M93S46-125MICROWIRE serial EEPROMSTMicroelectronics
STMicroelectronics

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche