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PDF EK6703 Data sheet ( Hoja de datos )
| Número de pieza | EK6703 | |
| Descripción | TFT LCD Timing Controller | |
| Fabricantes | Fiti | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EK6703 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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EK6703
TFT LCD Timing Controller
fitipower integrated technology Inc.
1
1 page  
fitipower
EK6703
4. PIN DESCRIPTION
Pin Name
DCLK
RI5 - RI0
GI5 - GI0
BI5 - BI0
DE
HSYNC
VSYNC
MODE
RES0
RESETB
STV1, STV2
VCLK
OEV
POL
REV
LD
RO5 - RO0
GO5 - GO0
BO5 - BO0
HCLK
DIO1, DIO2
UD
LR
TEST1, TEST2
TEST3
VDD
VSS
Pin No.
46
54 - 49
62 - 57
8-3
9
10
11
12
14
15
18, 47
19
20
21
22
23
36 - 41
30 - 35
24 - 29
42
43, 48
55
56
1, 2
13
16, 44, 63
17, 45, 64
Pin Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Power
Power
Description
Clock signal; latching data at the falling edge.
Data input.
6-bit data.
-
Data enable signal.
Horizontal sync input. Negative polarity.
Vertical sync input. Negative polarity.
DE/HV MODE select. Normally pulled high.
1: DE mode. 0:HV mode
Resolution Selection
1:800*600 and 800*480 0:640*480
Reset pin, active low. Normally pulled high.
Gate Start Pulse.
Gate driver shift clock.
Gate output off signal.
Polarity invert signal of Source Driver IC.
Data polarity invert control signal output.
Latch Pulse of Source Driver IC.
Data Output
Data Output
Data Output
Source driver shift clock.
Source Start Pulse.
UD = 1 STV1 Output STV2 Tristate
UD = 0 STV2 Output STV1 Tristate
LR = 1 DIO1 Output DIO2 Tristate
LR = 0 DIO2 Output
DIO1 Output
Test Pin, Please pull high or NC.
Please pull high in normal operation.
Power supply for digital circuits.
Ground pins for digital circuits.
2008/06/26
5
Rev. 1.1
5 Page 
fitipower
Output Signal Timing Chart
9. PACKAGE INFORMATION
EK6703
2008/06/26
11
Rev. 1.1
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet EK6703.PDF ] | |
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