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8T49N241 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 8T49N241
Beschreibung NG Universal Frequency Translator
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 30 Seiten
8T49N241 Datasheet, Funktion
FemtoClock® NG Universal Frequency
Translator
8T49N241
Datasheet
General Description
The 8T49N241 has one fractional-feedback PLL that can be used as
a jitter attenuator and frequency translator. It is equipped with one
integer and three fractional output dividers, allowing the generation
of up to four different output frequencies, ranging from 8kHz to 1GHz.
These frequencies are completely independent of each other, the
input reference frequencies and the crystal reference frequency. The
device places virtually no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error. The outputs may select among LVPECL, LVDS, HCSL or
LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis application,
including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and
SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The 8T49N241 accepts up to two differential or single-ended input
clocks and a fundamental-mode crystal input. The internal PLL can
lock to either of the input reference clocks or just to the crystal to
behave as a frequency synthesizer. The PLL can use the second
input for redundant backup of the primary input reference, but in this
case, both input clock references must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS), and generates an alarm when an input clock failure is
detected. Automatic and manual hitless reference switching options
are supported. LOS behavior can be set to support gapped or
un-gapped clocks.
The 8T49N241 supports holdover. The holdover has an initial
accuracy of ±50ppB from the point where the loss of all applicable
input reference(s) has been detected. It maintains a historical
average operating point for the PLL that may be returned to in
holdover at a limited phase slope.
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz.
The device supports Output Enable & Clock Select inputs and Lock,
Holdover & LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Programming with IDT’s Timing Commander software is
recommended for optimal device performance. Factory
pre-programmed devices are also available.
Applications
• OTN or SONET / SDH equipment
• Gigabit and Terabit IP switches / routers including Synchronous
Ethernet
• Video broadcast
Features
• Supports SDH/SONET and Synchronous Ethernet clocks including
all FEC rate conversions
• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz
• Operating Modes: Synthesizer, Jitter Attenuator
• Operates from a 10MHz to 50MHz fundamental-mode crystal or a
10MHz to 125MHz external oscillator
• Initial holdover accuracy of +50ppb.
• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks
• Accepts frequencies ranging from 8kHz to 875MHz
• Auto and manual clock selection with hitless switching
• Clock input monitoring including support for gapped clocks
• Phase-slope limiting and fully hitless switching options to control
output clock phase transients
• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz
(differential)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• One integer divider ranging from ÷4 to ÷786,420
• Three fractional output dividers (see Section, “Output Dividers”)
• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
• Optional fast-lock function
• Four General Purpose I/O pins with optional support for status &
control:
• Two Output Enable control inputs provide control over the four
clocks
• Manual clock selection control input
• Lock, Holdover and Loss-of-Signal alarm outputs
• Open-drain Interrupt pin
• Register programmable through I2C or via external I2C EEPROM
• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,
GPIO and control pins
• -40°C to 85°C ambient operating temperature
• Package: 40QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
REVISION 6, October 31, 2016






8T49N241 Datasheet, Funktion
8T49N241 Datasheet
Table 2. Pin Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%1
Symbol
CIN
RPULLUP
Parameter
Input Capacitance2
Input Pullup
Resistor
GPIO[3:0],
nRST, nWP,
SDATA, SCLK
Test Conditions
Input Pulldown
RPULLDOWN Resistor
S_A0, S_A1
LVCMOS Q[0]
VCCOX = 3.465V
LVCMOS Q[1:3]
VCCOX = 3.465V
LVCMOS Q[0]
VCCOX = 2.625V
LVCMOS Q[1:3]
Power Dissipation
CPD
Capacitance
LVCMOS Q[0]
(per output pair) LVCMOS Q[1:3]
VCCOX = 2.625V
VCCOX = 1.89V
VCCOX = 1.89V
LVDS, HCSL or
LVPECL Q[0]
VCCOX = 3.465V or 2.625V
LVDS, HCSL or
LVPECL Q[1:3]
VCCOX = 3.465V or 2.625V
VCCCS = 3.3V
GPIO[3:0]
VCCCS = 2.5V
ROUT
Output
Impedance
LVCMOS
Q[3:0], nQ[3:0]
VCCCS = 1.8V
VCCOX = 3.3V
VCCOX = 2.5V
VCCOX = 1.8V
NOTE 1: VCCOX denotes: VCCO0, VCCO1, VCCO2 or VCCO3.
NOTE 2: This specification does not apply to the OSCI or OSCO pins.
Minimum
Typical
3.5
Maximum Units
pF
51 k
51 k
11.5 pF
13 pF
10.5 pF
16 pF
11 pF
13 pF
2.5 pF
4.5 pF
26
30
42
18
22
30
©2016 Integrated Device Technology, Inc.
6
Revision 6, October 31, 2016

6 Page









8T49N241 pdf, datenblatt
8T49N241 Datasheet
Device Start-up & Reset Behavior
The 8T49N241 has an internal power-up reset (POR) circuit and a
Master Reset input pin nRST. If either is asserted, the device will be
in the Reset State.
For highly programmable devices, it’s common practice to reset the
device immediately after the initial power-on sequence. IDT
recommends connecting the nRST input pin to a programmable logic
source for optimal functionality. It is recommended that a minimum
pulse width of 10ns be used to drive the nRST input.
While in the reset state (nRST input asserted or POR active), the
device will operate as follows:
• All registers will return to & be held in their default states as
indicated in the applicable register description.
• All internal state machines will be in their reset conditions.
• The serial interface will not respond to read or write cycles.
• The GPIO signals will be configured as Output Enable inputs.
• All clock outputs will be disabled.
• All interrupt status and Interrupt Enable bits will be cleared,
negating the nINT signal.
Upon the later of the internal POR circuit expiring or the nRST input
negating, the device will exit reset and begin self-configuration.
The device will load an initial block of its internal registers using the
configuration stored in the internal One-Time Programmable (OTP)
memory. Once this step is complete, the 8T49N241 will check the
register settings to see if it should load the remainder of its
configuration from an external I2C EEPROM at a defined address or
continue loading from OTP, or both. See Section, “I2C Boot-up
Initialization Mode” for details on how this is performed.
Once the full configuration has been loaded, the device will respond
to accesses on the serial port and will attempt to lock the PLL to the
crystal and begin operation. Once the PLL is locked, all the outputs
derived from it will be synchronized and output phase adjustments
can then be applied if desired.
Serial Control Port Description
Serial Control Port Configuration Description
The device has a serial control port capable of responding as a slave
in an I2C compatible configuration, to allow access to any of the
internal registers for device programming or examination of internal
status. All registers are configured to have default values. See the
specifics for each register for details.
The device has the additional capability of becoming a master on the
I2C bus only for the purpose of reading its initial register
configurations from a serial EEPROM on the I2C bus. Writing of the
configuration to the serial EEPROM must be performed by another
device on the same I2C bus or pre-programmed into the device prior
to assembly.
I2C Mode Operation
The I2C interface is designed to fully support v1.2 of the I2C
Specification for Normal and Fast mode operation. The device acts
as a slave device on the I2C bus at 100kHz or 400kHz using the
address defined in the Serial Interface Control register (0006h), as
modified by the S_A0 & S_A1 input pin settings. The interface
accepts byte-oriented block write and block read operations. Two
address bytes specify the register address of the byte position of the
first register to write or read. Data bytes (registers) are accessed in
sequential order from the lowest to the highest byte (most significant
bit first). Read and write block transfers can be stopped after any
complete byte transfer. During a write operation, data will not be
moved into the registers until the STOP bit is received, at which point,
all data received in the block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 51ktypical.
Current Read
S Dev Addr + R A Data 0 A Data 1 A
A Data n Ā P
Sequential Read
S
Dev Addr + W
A Offset Addr MSB A Offset Addr LSB A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A Data n Ā P
Sequential Write
S Dev Addr + W A Offset Addr MSB A Offset Addr LSB A Data 0 A Data 1 A
A Data n A P
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
A = nonacknowledge
P = stop
Figure 5. I2C Slave Read and Write Cycle Sequencing
©2016 Integrated Device Technology, Inc.
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Revision 6, October 31, 2016

12 Page





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