PDF SI5376 Data sheet ( Hoja de datos )

Número de pieza	SI5376
Descripción	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Fabricantes	Silicon Laboratories
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Si5376 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features  Highly-integrated, 4 PLL clock  Supports all ITU G.709 and any multiplier/jitter attenuator custom FEC ratios (239/237,  Four independent DSPLLs support 255/238, 255/237, 255/236, 253/226) any-frequency synthesis and jitter  Integrated loop filter with attenuation programmable bandwidth  8 inputs/8 outputs  Simultaneous free-run and  Each DSPLL can generate any synchronous operation frequency from 2 kHz to 808 MHz  Automatic/manual hitless input clock from a 2 kHz to 710 MHz input switching  350 fs rms (12 kHz– 20 MHz) and  Selectable output clock signal format 410 fs rms (50 kHz–80 MHz) (LVPECL, LVDS, CML, CMOS) typical  LOL and interrupt alarm outputs  Meets ITU-T G.8251 and Telcordia  I2C programmable GR-253-CORE OC-192 jitter specifications  Single 1.8 V ±5% or 2.5 V ±10% operation with high PSRR on-chip  Programmable loop bandwidth: voltage regulator 60 Hz to 8 kHz  10x10 mm PBGA  Faster lock acquisition compared to the Si5374: <1.2 s  For a very low-loop BW version, see the Si5374 Applications  High-density, any-port, any-protocol,  1/2/4/8/10G Fibre Channel any-frequency line cards  GbE/10 GbE Synchronous Ethernet  ITU-T G.709 OTN custom FEC  Carrier Ethernet, multi-service  10/40/100G switches and routers  OC-48/192, STM-16/64  MSPP, ROADM, P-OTS, muxponders Description The Si5376 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub-1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts two input clocks ranging from 2 kHz to 710 MHz and generates two independent synchronous output clocks ranging from 2 kHz to 808 MHz. The device provides virtually any frequency translation combination across this operating range. For asynchronous, free-running clock generation applications, the Si5376’s reference oscillator can be used as a clock source for any of the four DSPLLs. The Si5376 input clock frequency and clock multiplication ratio are programmable through an I2C interface. The Si5376 is based on Silicon Laboratories’ third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components. Each DSPLL loop bandwidth is digitally-programmable, providing jitter performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on-chip voltage regulators with excellent PSRR. The Si5376 is ideal for providing clock multiplication and jitter attenuation in high-port-count optical line cards requiring independent timing domains. Ordering Information: See page 61. Rev. 1.0 9/12 Copyright © 2012 by Silicon Laboratories Si5376 1 page Si5376 Table 2. DC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C) Parameter Supply Current1 Symbol Test Condition Min Typ IDD LVPECL Format — 1000 622.08 MHz Out All CKOUTs Enabled LVPECL Format — 870 622.08 MHz Out 4 CKOUTs Enabled CMOS Format — 820 19.44 MHz Out All CKOUTs Enabled CMOS Format — 780 19.44 MHz Out 4 CKOUTs Enabled Disable Mode — 660 CKINn Input Pins2 Input Common Mode Voltage (Input Thresh- old Voltage) VICM 1.8 V ± 5% 2.5 V ± 10% 0.9 1 Input Resistance CKNRIN Single-ended 20 Single-Ended Input Voltage Swing (See Absolute Specs) VISE Differential Input Voltage Swing (See Absolute Specs) VID fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. 0.2 0.25 0.2 0.25 Output Clocks (CKOUTn)3,4 Common Mode CKOVCM Differential Output Swing CKOVD LVPECL 100  load line-to-line LVPECL 100  load line-to-line VDD – 1.42 1.1 Notes: 1. Current draw is independent of supply voltage. 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD = 2.5 V. 4. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. — — 40 — — — — — — Max 1100 970 940 880 — 1.4 1.7 60 — — — — VDD –1.25 1.9 Unit mA mA mA mA mA V V k VPP VPP VPP VPP V VPP Rev. 1.0 5 5 Page Si5376 Table 5. Performance Specifications VDD = 1.8 V ±5% or 2.5 V ±10%, TA = –40 to 85 °C Parameter Symbol Test Condition PLL Performance* Lock Time Output Clock Phase Change Closed Loop Jitter Peaking Jitter Tolerance Phase Noise fout = 622.08 MHz Spurious Noise Jitter Generation tLOCKMP tP_STEP JPK JTOL CKOPN SPSPUR JGEN Start of ICAL to of LOL, FASTLOCK disabled After clock switch f3  128 kHz Jitter Frequency Loop Bandwidth 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset Max spur @ n x F3 (n  1, n x F3 < 100 MHz) fIN = fOUT = 622.08 MHz, BW = 120 Hz LVPECL output 12 kHz–20 MHz 50 kHz–80 MHz *Note: fin = fout = 622.08 MHz; BW = 120 Hz; LVDS. Min Typ — 35 — 200 — 0.05 5000/BW — — –106 — –114 — –116 — –132 — –70 — 350 — 410 Max Unit 1200 ms — ps 0.1 dB — ns pk-pk — dBc/Hz — dBc/Hz — dBc/Hz — dBc/Hz — dBc 410 fs rms — fs rms Rev. 1.0 11 11 Page

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