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PDF SI3402-B Data sheet ( Hoja de datos )
| Número de pieza | SI3402-B | |
| Descripción | FULLY-INTEGRATED 802.3-COMPLIANT POE PD INTERFACE AND LOW-EMI SWITCHING REGULATOR | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si3402-B
FULLY-INTEGRATED 802.3-COMPLIANT POE PD INTERFACE
AND LOW-EMI SWITCHING REGULATOR
Features
Pin-compatible replacement for
the obsolete Si3402-A
IEEE 802.3 standard-compliant
solution, including pre-standard
(legacy) PoE support
Highly-integrated IC enables
compact solution footprints
Minimal external components
Integrated diode bridges and
transient surge suppressor
Integrated switching regulator
controller with on-chip power
FET
Integrated dual current-limited
hotswap switch
Programmable classification
circuit
Incorporates switcher EMI-
reduction techniques.
Supports non-isolated and
isolated switching topologies
Comprehensive protection
circuitry
Transient overvoltage
protection
Undervoltage lockout
Early power-loss indicator
Thermal shutdown protection
Foldback current limiting
Low-profile 5 x 5 mm 20-pin QFN
RoHS-compliant
Applications
Voice over IP telephones and
adapters
Wireless access points
Security cameras
Description
Point-of-sale terminals
Internet appliances
Network devices
High power applications
The Si3402 integrates all power management and control functions required in a
Power-over-Ethernet (PoE) powered device (PD) application. The Si3402
converts the high voltage supplied over the 10/100/1000BASE-T Ethernet
connection into a regulated, low-voltage output supply. The optimized architecture
of the Si3402 minimizes the solution footprint, reduces external BOM cost, and
enables the use of low-cost external components while maintaining high
performance. The Si3402 integrates the required diode bridges and transient
surge suppressor, thus enabling direct connection of the IC to the Ethernet RJ-45
connector. The switching power FET and all associated functions are also
integrated. The integrated switching regulator supports isolated (flyback) and non-
isolated (buck) converter topologies. The Si3402 supports IEEE 802.3at Type 1
Powered Device applications. Standard external resistors connected to the
Si3402 provide the proper 802.3 signatures for the detection function and
programming of the classification mode. Startup circuits ensure well-controlled
initial operation of both the hotswap switch and the voltage regulator. The Si3402
is available in a low-profile, 20-pin, 5 x 5 mm QFN package. The Si3402 is
designed for IEEE 802.3at Type 1 (Class 3 and below) applications. The Si3402-B
is a pin-compatible replacement of the obsolete Si3402-A. PCB layouts designed
for Si3402-A can be reused with Si3402-B, but some component value changes
are required.
Ordering Information:
See page 18.
Pin Assignments
5 x 5 mm QFN
(Top View)
20 19 18 17 16 15
EROUT 1
SSFT* 2
VDD 3
ISOSSFT* 4
VNEG
(PAD)
14 CT1
13 CT2
12 VPOSF
11 SP1
5 6 7 8 9 10
Note:
Original pin names shown for compatibil-
ity reasons, but SSFT, ISOSSFT, VPOSS,
and VSS1 are not internally connected.
Rev. 1.0 11/15
Copyright © 2015 by Silicon Laboratories
Si3402-B
1 page  
Si3402-B
Table 3. Surge Immunity Ratings1,2,3
Type
CDE4
Description
Cable discharge event tolerance
Rating
–3.5 to 3.5
Unit
kV
Air discharge (IEC 61000-4-2)
ESD (System-Level)
Contact discharge (IEC 61000-4-2)
–16.5 to 16.5
–8 to 8
kV
kV
ESD (CDM)
JEDEC (JESD22-C101C)
–750 to 750
V
ESD (HBM)
JEDEC (JESD22-A114E)
–2000 to 2000 V
Telephony Voltage
Compatibility
IEEE 802.3, Clause 33.5.6
175 Vp
Notes:
1. Permanent device damage may occur if the maximum ratings are exceeded. Functional operation should be restricted
to those conditions specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may adversely affect device reliability.
2. For more information regarding system-level surge tolerance, refer to “AN315: Robust Electrical Surge Immunity for
PoE PDs through Integrated Protection”.
3. Designs must be compliant with the PCB layout and external component recommendations outlined in the Si3402 EVB
User Guide and application note, “AN956: Using the Si3402-B PoE PD Controller in Isolated and Non-Isolated
Designs”.
4. J. Deatherage and D. Jones, “Multiple Factors Trigger Cable Discharge Events in Ethernet LANs,” Electronic Design
Dec. 4, 2000.
Rev. 1.0
5
5 Page 
Si3402-B
Table 9. Hotswap Interface Modes
Input Voltage
(|CT1-CT2| or |SP1-SP2|)
Si3402 Mode
0 to 2.7 V
Inactive
2.7 to 11 V
Detection signature
11 to 14 V
Detection turns off and
internal bias starts
14 to 22 V
22 to 42 V
42 up to 57 V
57 down to 36 V
Classification signature
Transition region
Switcher operating mode
(hysteresis limit based on
rising input voltage)
Switcher operating mode
(hysteresis limit based on
falling input voltage)
3.2.1. Rectification Diode Bridges and
Surge Suppressor
The 802.3 specification defines the input voltage at the
RJ-45 connector of the PD with no reference to polarity.
In other words, the PD must be able to accept power of
either polarity at each of its inputs. This requirement
necessitates the use of two sets of diode bridges, one
for the CT1 and CT2 pins and one for the SP1 and SP2
pins to rectify the voltage. Furthermore, the standard
requires that a PD withstand a high-voltage transient
surge consisting of a 1000 V common-mode impulse
with 300 ns rise time and 50 µs half fall time. Typically,
the diode bridge and the surge suppressor have been
implemented externally, adding cost and complexity to
the PD system design.
The diode bridge* and the surge suppressor have been
integrated into the Si3402, thus reducing system cost
and design complexity.
*Note: Silicon Laboratories recommends that on-chip diode
bridges be bypassed when >7 W of output power is
required.
By integrating the diode bridges, the Si3402 gains
access to the input side of the diode bridge. Monitoring
the voltage at the input of the diode bridges instead of
the voltage across the load capacitor provides the
earliest indication of a power loss. This true early power
loss indicator, PLOSS, provides a local microcontroller
time to save states and shut down gracefully before the
load capacitor discharges below the minimum 802.3-
specified operating voltage of 36 V. Integration of the
surge suppressor enables optimization of the clamping
voltage and guarantees protection of all connected
circuitry.
As an added benefit, the transient surge suppressor,
when tripped, actively disables the hotswap interface
and switching regulator, preventing downstream circuits
from encountering the high-energy transients.
3.2.2. Detection
In order to identify a device as a valid PD, a PSE will
apply a voltage in the range of 2.8 to 10 V on the cable
and look for the 24.3 k signature resistor. The Si3402
will react to voltages in this range by connecting an
external 24.3 k resistor between VPOS and VNEG. This
external resistor and internal low-leakage control
circuitry create the proper signature to alert the PSE
that a valid PD has been detected and is ready to have
power applied. The internal hotswap switch is disabled
during this time to prevent the switching regulator and
attached load circuitry from generating errors in the
detection signature.
Since the Si3402 integrates the diode bridges, the IC
can compensate for the voltage and resistance effects
of the diode bridges. The 802.3 specification requires
that the PSE use a multi-point, V/I measurement
technique to remove the diode-induced dc offset from
the signature resistance measurement. However, the
specification does not address the diode's nonlinear
resistance and the error induced in the signature
resistor measurement. Since the diode's resistance
appears in series with the signature resistor, the PD
system must find some way of compensating for this
error. In systems where the diode bridges are external,
compensation is difficult and suffers from errors. Since
the diode bridges are integrated in the Si3402, the IC
can compensate for this error by offsetting resistance
across all operating conditions and thus meeting the
802.3 requirements. An added benefit is that this
function can be tested during the IC’s automated testing
step, guaranteeing system compliance when used in
the final PD application. For more information about
supporting higher-power applications (above 12.95 W),
see “AN313: Using the Si3402 in High Power
Applications” and “AN314: Power Combining Circuit for
PoE for up to 18.5 W Output”.
3.2.3. Classification
Once the PSE has detected a valid PD, the PSE may
classify the PD for one of five power levels or classes. A
class is based on the expected power consumption of
the powered device. An external resistor sets the
nominal class current that can then be read by the PSE
to determine the proper power requirements of the PD.
When the PSE presents a fixed voltage between 15.5 V
and 20.5 V to the PD, the Si3402 asserts the class
current from VPOS through the RCL resistor. The
resistor values associated with each class are shown in
Table 10.
Rev. 1.0
11
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