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PDF SI554 Data sheet ( Hoja de datos )
| Número de pieza | SI554 | |
| Descripción | QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si554
REVISION D
QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL
OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ
Features
Available with any-rate output
Internal fixed crystal frequency
frequencies from 10–945 MHz and
ensures high reliability and low
selected frequencies to 1.4 GHz
aging
Four selectable output frequencies Available CMOS, LVPECL,
3rd generation DSPLL® with superior LVDS, and CML outputs
jitter performance
3.3, 2.5, and 1.8 V supply options
3x better frequency stability than Industry-standard 5 x 7 mm
SAW-based oscillators
package and pinout
Pb-free/RoHS-compliant
Applications
SONET/SDH
xDSL
10 GbE LAN / WAN
Description
Low jitter clock generation
Optical modules
Clock and data recovery
The Si554 quad-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL® circuitry to provide a very low jitter clock for all output frequencies.
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory-programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
VDD CLK- CLK+
Si5602
Ordering Information:
See page 10.
Pin Assignments:
See page 9.
(Top View)
VC 1
FS[1]
7
6
VDD
OE 2
5 CLK–
GND 3
8
FS[0]
4
CLK+
Any-rate
FS1
Fixed
Frequency XO
10–1400 MHz
DSPLL®
Clock Synthesis
FS0
ADC
Rev. 1.1 4/13
Vc OE GND
Copyright © 2013 by Silicon Laboratories
Si554
1 page  
Si554
Table 5. CLK± Output Phase Jitter (Continued)
Parameter
Phase Jitter (RMS)1,2,3,4,5
for FOUT of 125 to 500 MHz
Symbol
Test Condition
J Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Min
—
—
Typ
0.37
0.33
Max Units
— ps
—
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
—
0.37
0.4 ps
50 kHz to 80 MHz (OC-192) — 0.33 —
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
—
0.43
—
ps
50 kHz to 80 MHz (OC-192) — 0.34 —
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
—
0.50
—
ps
50 kHz to 80 MHz (OC-192) — 0.34 —
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
—
0.59
—
ps
50 kHz to 80 MHz (OC-192) — 0.35 —
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
—
1.00
—
ps
50 kHz to 80 MHz (OC-192) — 0.39 —
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Rev. 1.1
5
5 Page 
Si554
4. Package Outline and Suggested Pad Layout
Figure 2 illustrates the package details for the Si554. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 2. Si554 Outline Diagram
Table 12. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A 1.50 1.65 1.80
b 1.30 1.40 1.50
b1 0.90 1.00 1.10
c 0.50 0.60 0.70
c1 0.30 — 0.60
D 5.00 BSC
D1 4.30 4.40 4.50
e 2.54 BSC
E 7.00 BSC
E1 6.10 6.20 6.30
H 0.55 0.65 0.75
L 1.17 1.27 1.37
L1 1.07 1.17 1.27
p 1.80 — 2.60
R 0.70 REF
aaa — — 0.15
bbb — — 0.15
ccc — — 0.10
ddd — — 0.10
eee — — 0.05
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.1
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet SI554.PDF ] | |
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