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F25D64QA Schematic ( PDF Datasheet ) - Elite Semiconductor

Teilenummer F25D64QA
Beschreibung 64 Mbit Serial Flash Memory
Hersteller Elite Semiconductor
Logo Elite Semiconductor Logo 




Gesamt 30 Seiten
F25D64QA Datasheet, Funktion
ESMT
Flash
FEATURES
Single supply voltage 1.65~2V
Speed
- Fast Read for SPI mode
- Read max frequency: 33MHz
- Fast Read max frequency: 104MHz
- Fast Read Dual/Quad max frequency: 84MHz/104MHz
(168MHz equivalent Dual SPI;
416MHz equivalent Quad SPI)
- Fast Read for QPI mode
- Fast Read max frequency: 84MHz
- Fast Read Quad max frequency: 104MHz
(416MHz equivalent Quad QPI)
- 8/ 16/ 32/ 64 byte Wrap-Around Burst Read Mode
Low power consumption
- Active current: 15mA (typ.)
- Standby current: 50 μ A (typ.)
- Deep Power Down current: 5 μ A (typ.)
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Page programming time: 1.2 ms (typical)
Page Programming
- 256 byte per programmable page
F25D64QA
64 Mbit Serial Flash Memory
with Dual and Quad
Program/Erase Suspend
Erase
- Chip Erase time 38 sec (typical)
- 64K bytes Block Erase time 0.5 sec (typical)
- 32K bytes Block Erase time 250 ms (typical)
- 4K bytes Sector Erase time 60 ms (typical)
Status and Security Register Feature
Command Reset
Advanced Security Features
- Flexible Block Protection (BP0-BP3)
Lockable 512 bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
Support Serial Flash Discoverable Parameters (SFDP) mode
Write Protect ( WP )
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25D64QA –104PAIG
Speed
104MHz
F25D64QA –104VAIG
104MHz
F25D64QA –104HIG
104MHz
Package
8-lead
SOIC
8-lead
VSOP
8-contact
WSON
200 mil
208mil
6x5 mm
Comments
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2013
Revision: 1.1
1/63






F25D64QA Datasheet, Funktion
ESMT
F25D64QA
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Bit Name
Function
Status Register
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
2 BP0 Indicate current level of block write protection (See Table 3)
3 BP1 Indicate current level of block write protection (See Table 3)
4 BP2 Indicate current level of block write protection (See Table 3)
5 BP3 Indicate current level of block write protection (See Table 3)
6
QE
1 = Quad enabled
0 = Quad disabled
7
BPL
1 = BP3, BP2,BP1,BP0 are read-only bits
0 = BP3, BP2,BP1,BP0 are read/writable
Note:
1. BUSY and WEL are read only.
2. BP0~3, QE and BPL bits are non-volatile.
Default at
Power-up
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Page Program instruction completion
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write Status Register instructions completion
Signal Block Lock (SBLK) instruction completion
Signal Block Unlock (SBULK) instruction completion
Gang Block Lock (GBLK) instruction completion
Gang Block Unlock (GBULK) instruction completion
Write Security Register (WRSCUR) instruction completion
Write Protect Selection (WPSEL) instruction completion
BUSY
The BUSY bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the BUSY bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Quad Enable (QE)
When the Quad Enable bit is reset to “0” (factory default), WP
and HOLD pins are enabled. When QE pin is set to “1”, Quad
SIO2 and SIO3 are enabled. (The QE should never be set to “1”
during standard and Dual SPI operation if the WP and HOLD
pins are tied directly to the VDD or VSS.). When in QPI mode, QE
bit is not required for setting.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2013
Revision: 1.1
6/63

6 Page









F25D64QA pdf, datenblatt
ESMT
F25D64QA
Operation
Fast Read
Fast Read Quad I/O12, 14
(4READ)
Sector Erase4 - 4KB (SE)
Block Erase 32KB 5 (BE32K)
Block Erase5 (BE)
Chip Erase (CE)
Program / Erase Suspend
Program / Erase Resume
Page Program (PP)
Mode Bit Reset16
Read Status Register
(RDSR) 7
Write Status Register
(WRSR) 10
Write Enable (WREN) 10
Write Disable (WRDI)
Read Electronic Signature
(RES) 8
RES in secured OTP mode &
not lock down
RES in secured OTP mode &
lock down
Deep Power Down (DP)
Release from Deep Power
Down (RDP)
Exit OTP (EXSO)
Enter secured OTP mode
(ENSO)
Read Security Register
(RDSCUR)
Write Security Register
(WRSCUR)
Reset Enable (RSTEN)
Reset Memory (RST) 6
Signal Block Lock (SBLK)
Signal Block Unlock (SBULK)
Block Protect Read
(RDBLOCK)
Gang Block Lock (GBLK)
Gang Block Unlock (GBULK)
Write Protect Selection
(WPSEL)
Set Burst Length (SBL)
QPI ID Read (QPIID) 9
Reset Quad I/O (RSTQIQ)
NOP
Table 6-2: Device Operation Instruction (QPI)
Max.
Freq
84MHz
104MHz
1
SIO
0BH
EBH
20H
52H
D8H
60H /
C7H
B0H
30H
2
SIO
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
-
-
-
3
SIO
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
-
-
-
QPI Bus Cycle 1~3
456
SIO
A7-A0
SIO
M7-M0
SIO
X
A7-A0 M7-M0
X
A7-A0
A7-A0
A7-A0
-
-
-
-
-
-
---
---
---
02H
FFH
05H
01H
06H
04H
ABH
A23-A16 A15-A8
FFH
DOUT
(S7-S0)
DIN
(S7-S0)
-
-
X
FFH
-
-
-
-
X
A7-A0
FFH
-
-
-
-
X
DIN0
-
-
-
-
-
37H
DIN1
-
-
-
-
-
-
ABH
X
X
X 77H -
ABH
X
X
X F7H -
104MHz B9H
-
-
-
-
-
ABH
-
-
-
-
-
C1H
-
-
-
-
-
B1H - - - - -
2BH
2FH
66H
99H
36H
39H
3CH
7EH
98H
68H
C0H
AFH
F5H
00H
DOUT
-
-
-
-
A23-A16
A23-A16
A23-A16
-
-
-
DIN
8CH
-
-
-
-
-
A15-A8
A15-A8
A15-A8
-
-
-
-
25H
-
-
-
-
-
-
A7-A0
A7-A0
A7-A0
-
-
-
-
37H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
SIO
DOUT0
X
-
-
-
-
-
-
DIN2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8
SIO
DOUT1
DOUT0
-
-
-
-
-
-
DIN3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N
SIO
cont.
cont.
-
-
-
-
-
-
Up to
256
bytes
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Notes:
1.
2.
3.
4.
Operation: SIN = Serial In, SOUT = Serial Out, SIO = Serial In/Out.
X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
One SPI bus cycle is eight clock periods; one QPI bus cycle is two clock periods.
4K byte Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2013
Revision: 1.1
12/63

12 Page





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