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F25L16PA Schematic ( PDF Datasheet ) - Elite Semiconductor

Teilenummer F25L16PA
Beschreibung 16 Mbit Serial Flash Memory
Hersteller Elite Semiconductor
Logo Elite Semiconductor Logo 




Gesamt 30 Seiten
F25L16PA Datasheet, Funktion
ESMT
Flash
F25L16PA (2S)
16 Mbit Serial Flash Memory
with Dual
„ FEATURES
y Single supply voltage 2.7~3.6V
y Standard and Dual
y Speed
- Read max frequency: 50MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz / 100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI)
y Low power consumption
- Active current: 23.5 mA (max.)
- Standby current: 25 μ A (max.)
- Deep Power Down current: 10 μ A (max.)
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Page programming time: 1.5 ms (typical)
y Erase
- Chip Erase time 10 sec (typical)
- 64K bytes Block Erase time 1 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 120 ms (typical)
y Page Programming
- 256 byte per programmable page
y Lockable 512 bytes OTP security sector
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
„ ORDERING INFORMATION
Product ID
Speed
F25L16PA –50PG2S
50MHz
F25L16PA –86PG2S
86MHz
F25L16PA –100PG2S 100MHz
F25L16PA –50PAG2S 50MHz
F25L16PA –86PAG2S 86MHz
F25L16PA –100PAG2S 100MHz
F25L16PA –50PHG2S 50MHz
F25L16PA –86PHG2S 86MHz
F25L16PA –100PHG2S 100MHz
F25L16PA –50DG2S
50MHz
F25L16PA –86DG2S
86MHz
F25L16PA –100DG2S 100MHz
F25L16PA –50HG2S
50MHz
F25L16PA –86HG2S
86MHz
F25L16PA –100HG2S 100MHz
Package
Comments
8-lead
SOIC
150 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
16-lead
SOIC
300 mil
Pb-free
8-pin
PDIP
300 mil
Pb-free
8-contact
WSON
6x5 mm
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
1/42






F25L16PA Datasheet, Funktion
ESMT
F25L16PA (2S)
„ SECTOR STRUCTURE
64KB
Block
31
30
29
28
27
26
32KB
Block
63
62
61
60
59
58
57
56
55
54
53
52
Table 1: F25L16PA Sector Address Table
Sector
511
:
504
503
:
496
495
:
488
487
:
480
479
:
472
471
:
464
463
:
456
455
:
448
447
:
440
439
:
432
431
:
424
423
:
416
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
1FF000H – 1FFFFFH
:
1F8000H – 1F8FFFH
1F7000H – 1F7FFFH
:
1F0000H – 1F0FFFH
1EF000H – 1EFFFFH
:
1E8000H – 1E8FFFH
1E7000H – 1E7FFFH
:
1E0000H – 1E0FFFH
1DF000H – 1DFFFFH
:
1D8000H – 1D8FFFH
1D7000H – 1D7FFFH
:
1D0000H – 1D0FFFH
1CF000H – 1CFFFFH
:
1C8000H – 1C8FFFH
1C7000H – 1C7FFFH
:
1C0000H – 1C0FFFH
1BF000H – 1BFFFFH
:
1B8000H – 1B8FFFH
1B7000H – 1B7FFFH
:
1B0000H – 1B0FFFH
1AF000H – 1AFFFFH
:
1A8000H – 1A8FFFH
1A7000H – 1A7FFFH
:
1A0000H – 1A0FFFH
Block Address
A20 A19 A18 A17 A16
11111
11110
11101
11100
11011
11010
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
6/42

6 Page









F25L16PA pdf, datenblatt
ESMT
Protection Level
0
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
All Blocks
Bottom 1/2
Bottom 3/4
Bottom 7/8
Bottom 15/16
Bottom 31/32
All Blocks
F25L16PA (2S)
Table 3: F25L16PA Block Protection Table
Status Register Bit
BP3 BP2 BP1 BP0
Protected Memory Area
Block Range
Address Range
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
None
Block 31
Block 30~31
Block 28~31
Block 24~31
Block 16~31
Block 0~31
Block 0~31
Block 0~31
Block 0~31
Block 0~15
Block 0~23
Block 0~27
Block 0~29
Block 0~30
Block 0~31
None
1F0000H – 1FFFFFH
1E0000H – 1FFFFFH
1C0000H – 1FFFFFH
180000H – 1FFFFFH
100000H – 1FFFFFH
000000H – 1FFFFFH
000000H – 1FFFFFH
000000H – 1FFFFFH
000000H – 1FFFFFH
000000H – 0FFFFFH
000000H –17FFFFH
000000H –1BFFFFH
000000H – 1DFFFFH
000000H – 1EFFFFH
000000H – 1FFFFFH
Block Protection (BP3, BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
BP3, BP2, BP1 and BP0 bits as long as WP is high or the
Block- Protection-Look (BPL) bit is 0. Chip Erase can only be
executed if BP3, BP2, BP1 and BP0 bits are all 0. The factory
default setting for Block Protection Bit (BP3 ~ BP0) is 0.
Block Protection Lock-Down (BPL)
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When
the WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
12/42

12 Page





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