PDF F25L04PA Data sheet ( Hoja de datos )

Número de pieza	F25L04PA
Descripción	3V Only 4 Mbit Serial Flash Memory
Fabricantes	Elite Semiconductor
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ESMT Flash F25L04PA 3V Only 4 Mbit Serial Flash Memory with Dual Output  FEATURES  Single supply voltage 2.3~3.6V  Standard, Dual SPI  Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 86MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 86MHz/ 100MHz (100MHz / 172MHz/ 200MHz equivalent Dual SPI)  Low power consumption - Active current: 25 mA - Standby current: 30 μ A - Deep Power Down current: 5 μ A  Reliability - 100,000 typical program/erase cycles - 20 years Data Retention  Program - Byte programming time: 7 μ s (typical) - Page programming time: 1.5 ms (typical)  Erase - Chip erase time 3.5 sec (typical) - Block erase time 0.75 sec (typical) - Sector erase time 150 ms (typical)  Page Programming - 256 byte per programmable page  SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3  End of program or erase detection  Write Protect ( WP )  Hold Pin ( HOLD )  All Pb-free products are RoHS-Compliant  ORDERING INFORMATION Product ID F25L04PA –50PG F25L04PA –86PG F25L04PA –100PG F25L04PA –50PAG F25L04PA –86PAG F25L04PA –100PAG F25L04PA –50DG F25L04PA –86DG F25L04PA –100DG F25L04PA –50HG F25L04PA –86HG F25L04PA –100HG Speed 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz Package Comments 8-lead SOIC 150 mil Pb-free 8-lead SOIC 200 mil Pb-free 8-pin PDIP 300 mil Pb-free 8-contact WSON 6x5 mm Pb-free  GENERAL DESCRIPTION The F25L04PA is a 4Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 2,048 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device features sector erase architecture. The memory array Elite Semiconductor Memory Technology Inc. is divided into 128 uniform sectors with 4K byte each; 8 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. Publication Date: Aug. 2012 Revision: 1.1 1/34 1 page ESMT  SECTOR STRUCTURE Block 7 6 5 4 3 2 1 0 Table 1: F25L04PA Sector Address Table Sector 127 : 112 111 : 96 95 : 80 79 : 64 63 : 48 47 : 32 31 : 16 15 : 0 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB Address range 07F000H – 07FFFFH : 070000H – 070FFFH 06F000H – 06FFFFH : 060000H – 060FFFH 05F000H – 05FFFFH : 050000H – 050FFFH 04F000H – 04FFFFH : 040000H – 040FFFH 03F000H – 03FFFFH : 030000H – 030FFFH 02F000H – 02FFFFH : 020000H – 020FFFH 01F000H – 01FFFFH : 010000H – 010FFFH 00F000H – 00FFFFH : 000000H – 000FFFH Block Address A18 A17 A16 1 11 1 10 1 01 1 00 0 11 0 10 0 01 0 00 F25L04PA Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012 Revision: 1.1 5/34 5 Page ESMT F25L04PA Read (33MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 07FFFFH had been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23 -A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. Figure 2: Read Sequence Fast Read (50 MHz ~ 100 MHz) The Fast Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read cycle. See Figure 3 for the Fast Read sequence. Following a dummy byte (8 clocks input dummy cycle), the Fast Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 07FFFFH has been read, the next output will be from address location 000000H. CE MODE3 SCK MODE0 0 12 3 45 67 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI 0B ADD. ADD. A DD. MSB MSB SO HIGH IMPENANCE Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 3: Fast Read Sequence Elite Semiconductor Memory Technology Inc. X N D OU T MSB N+1 DOUT N+2 DOUT N+3 D OU T N+4 D OU T Publication Date: Aug. 2012 Revision: 1.1 11/34 11 Page

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