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A31S Schematic ( PDF Datasheet ) - Allwinner Technology

Teilenummer A31S
Beschreibung quad-core phablet processor
Hersteller Allwinner Technology
Logo Allwinner Technology Logo 




Gesamt 30 Seiten
A31S Datasheet, Funktion
A31s
Datasheet
Revision 1.4
Feb 14, 2014
Copyright © 2014 Allwinner Technology. All Rights Reserved.






A31S Datasheet, Funktion
2 FEATURES
CPU Architecture
Quad Cortex-A7
- ARMv7 ISA standard ARM instruction set plus
Thumb2, Jazeller RCT
- NEON SIMD coprocessor and VFPv4 for each
CPU
- TrustZone security technology
- Hardware virtualization
- Large Physical Address Extensions(LPAE)
- Debug and trace features
- One general timer for an individual CPU
- 32KB instruction and 32KB data L1 cache for an
individual CPU
- Shared 1MB L2 cache
CPUS
- Support 4KB I-cache
- Support 64KB SRAM (instruction space)
- Support 64KB secure SRAM (data space)
GRAPHIC ENGINE
3D
- PowerVR SGX544MP2 GPU
- Support OpenGL ES 2.0, OpenVG 1.1, OpenCL
1.1, and DX 9.3 standards
2D
- Support BLT and ROP2/3/4, scaling function with
4x4 taps and 32 phases
- Support 90/180/270 degree rotation
- Support mirror/alpha (plane and pixel alpha)/
color key
- Format conversion: ARGB 8888/4444/1555,
RGB565, Mono 1/2/4/8 bpp, Palette 1/2/4/8 bpp
(input only), YUV 444/422/420
- Support command queue
SYSTEM RESOURCES
Timer
- 6 timers: clock source can be switched over
24M/32K for all timers, and external signals can
function as clock source for timer4/5
- 33-bit AVS counter
- 4 watchdogs to generate reset signal or
interrupts
GIC
- Support 16 SGIs, 16 PPIs, and 128 SPIs
- Support ARM architecture security extensions
- Support ARM architecture virtualization
extensions
- Support uniprocessor and multiprocessor
environments
HS-Timer
- 4 channels
- Clock source fixed to AHB, and pre-scale ranges
from 1 to 16
- 56-bit counter that can be separated to 24-bit
high register and 32-bit low register
DMA
- 16 channels
- Support data width of 8/16/32 bits
- Support linear and IO address modes
- DMA channels can be paused during data
transfer if necessary
RTC
- Real time registers for second, minute, hour, day,
month and year
- Two alarms based on seconds and weeks
- 16 general purpose registers
CCU
- programmable PLLs
MEMORY SUBSYSTEM
Internal Boot ROM
- Support system boot from 8-bit NAND Flash, SPI
Nor Flash (SPI0) and SD/TF/8-bit eMMC
(SDC0/2)
- Support system code download via USB DRD
(USB0)
DRAM
- Support DDR3/DDR3L/LPDDR2
- Support 32-bit bus width
A31s Datasheet (Revision1.4)
Copyright © 2014 Allwinner Technology. All Rights Reserved.
Page 6

6 Page









A31S pdf, datenblatt
Ball#
Pin Name1
W5
P6,R6,T6,T7,U6,U7,U8,
V6,V7,W7,
U9
GPIO A7
F18
E19
G18
F19
D20
H18
J18
C20
C21
C22
J19
H19
G19
D21
E20
G20
F20
E21
E22
F21
F22
H20
G21
H21
J21
J20
H22
J22
M17,N17
GPIO B7
B19
C19
A20
B20
A21
B21
A22
SVREF
VCC-DRAM
(10)
VDD-DLL
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
VCC-PA
PB0
PB1
PB2
PB3
PB4
PB5
PB6
Default
Function2
DRAM
DRAM
DRAM
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
POWER
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Type3
Default
IO State4
Default
Buffer
Pull Up/Down5 Strength6 (mA)
Power Supply
P-
P-
P-
-
-
-
-
-
-
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
P-
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
I/O DIS
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
Z
Z
Z
Z
Z
Z
Z
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20 VCC-PA
20
20
20
20
20
20
20
20
20
20
20
20
20
-
20
20
20
20 VCC-PB
20
20
20
A31s Datasheet (Revision1.4)
Copyright © 2014 Allwinner Technology. All Rights Reserved.
Page 12

12 Page





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