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PDF 2EDL05I06BF Data sheet ( Hoja de datos )
| Número de pieza | 2EDL05I06BF | |
| Descripción | 600V half bridge gate drive IC | |
| Fabricantes | Infineon | |
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EiceDRIVER™ Compact
High voltage gate driver IC
2EDL family
600 V half bridge gate drive IC
2EDL05I06PF
2EDL05I06PJ
2EDL05I06BF
2EDL05N06PF
2EDL05N06PJ
EiceDRIVER™ Compact
Final datasheet
<Revision 2.6>, 01.06.2016
Final
Industrial Power Control
1 page  
EiceDRIVER™ Compact
2EDL family
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Typical Application SO8 / SO14 package 0.5 A..................................................................................8
Block diagram for 2EDL05x06Py .........................................................................................................9
Pin Configuration of 2EDL family .......................................................................................................10
Input pin structure...............................................................................................................................11
Input filter timing diagram ...................................................................................................................11
Timing of short pulse suppression .....................................................................................................18
Timing of of internal deadtime............................................................................................................18
Input to output propagation delay times and switching times definition .............................................18
Operating areas (IGBT UVLO levels).................................................................................................19
Operating areas (MOSFET UVLO levels) ..........................................................................................19
Output pulse width timing and matching delay timing diagram for positive logic...............................19
Package drawing................................................................................................................................20
PCB reference layout left: Reference layout right: detail of footprint ..............................................20
Package drawing................................................................................................................................21
PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint ....21
Final datasheet
5 <Revision 2.6>, 01.06.2016
5 Page 
EiceDRIVER™ Compact
2EDL family
HINx
LINx
Figure 4 Input pin structure
2EDL-family
ILIN
IHIN
Vcc VIH; VIL
INPUT
NOISE
FILTER
VZ=5.25 V
3.2.3
Input filter time
a) tFILIN
b) tFILIN
LIN
LO
low
HIN
LIN
high
HO
LO
Figure 5 Input filter timing diagram
Short pulses are suppressed by means of an input filter. All IC, which have undervoltage lockout (UVLO)
thresholds for MOSFET, have an input filter time of tFILIN = 75ns typ. and 150ns max. All IC having UVLO
thresholds for IGBT have filter times of tFILIN = 150ns min and 200ns typ.
3.3 VDD and GND
VDD is the low side supply and it provides power to both the input logic and the low side output power stage.
The input logic is referenced to GND ground as well as the under-voltage detection circuit. Output power stage
is also referenced to GND ground.
The undervoltage lockout circuit enables the device to operate at power on when a typical supply voltage higher
than VDDUV+ is present. Please see section 3.6 “Undervoltage lockout”” for further information.
A filter time of typ. 1.8µs1 helps to suppress noise from the UVLO circuit, so that negative going voltage spikes
at the supply pins will avoid parasitic UVLO events.
3.4 VB and VS (High Side Supplies)
VB to VS is the high side supply voltage. The high side circuit can float with respect to GND following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VDD. A filter time of typ. 1.8µs1 helps to suppress
noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO
events.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VDDUV+ is present. Please see section 3.6 “Undervoltage lockout” for further information. Details on bootstrap
supply section and transient immunity can be found in application note EiceDRIVER™ 2EDL family: Technical
description.
3.5 LO and HO (Low and High Side Outputs)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive for IGBT
and MOSFET devices. Low side output is state triggered by the respective input, while high side output is edge
triggered by the respective input. In particular, after an undervoltage condition of the VBS supply, a new turn-on
signal (edge) is necessary to activate the high side output. In contrast, the low side outputs switch to the state of
their respective inputs after an undervoltage condition of the VDD supply.
The output current specification IO+ and IO- is defined in a way, which considers the power transistors miller
voltage.This helps to design the gate drive better in terms of the application needs. Nevertheless, the devices
are also characterised for the value of the pulse short circuit value IOpk+ and IOpk–.
Final datasheet
11 <Revision 2.6>, 01.06.2016
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 2EDL05I06BF.PDF ] | |
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