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TC62D748CFG Schematic ( PDF Datasheet ) - Toshiba

Teilenummer TC62D748CFG
Beschreibung 16-Output Constant Current LED Driver
Hersteller Toshiba
Logo Toshiba Logo 




Gesamt 23 Seiten
TC62D748CFG Datasheet, Funktion
TC62D748CFG
TOSHIBA CDMOS Integrated Circuit Silicon Monolithic
TC62D748CFG
16-Output Constant Current LED Driver
The TC62D748CFG is a constant-current driver for LED and
LED display lighting applications.
The output current from each of the 16 outputs is
programmable via a single external resistor.
The TC62D748CFG contains a 16-channel shift register, a
16-channel latch, a 16-channel AND gate and a 16-channel
constant-current output.
Fabricated with a CMOS process, the TC62D748CFG allows
high-speed data transfer.
It operates with a 3.3- or 5-V power supply.
SSOP24-P-300-1.00B
Weight: 0.29 g (Typ.)
Features
Supply voltages
: VDD = 3.0 V to 5.0 V
16-output built-in
Output current setup range
: IOUT = 1.5 to 90 mA
Constant current output accuracy (@ REXT = 1.2 kΩ, VOUT = 1.0 V, VDD = 3.3 V, 5.0 V)
: S rankbetween outputs ± 1.5 % (max)
: S rankbetween devices: ± 1.5 % (max)
: N rankbetween outputs ± 2.5 % (max)
: N rankbetween devices: ± 2.5 % (max)
Output voltage
: VOUT = 17 V (max)
High-speed output switching
: twOE(L) = 25 ns (min), tor = 30ns (typ.), tof = 10ns (typ.)
There is TC62D749 as an output switching high-speed version of this product.
I/O interface
: CMOS interfaces (Schmitt trigger input)
Data transfer frequency
: fSCK = 25 MHz (max)
Operation temperature range
: Topr = −40 to 85 °C
Power-on-reset function built-in. (When the power supply is turned on, internal data is reset)
Package
: SSOP24-P-300-1.00B
For detailed part naming conventions, contact your local Toshiba sales representative or distributor.
1 2011-12-14






TC62D748CFG Datasheet, Funktion
TC62D748CFG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Supply voltage
Output current
Logic input voltage
Output voltage
Operating temperature
Storage temperature
Thermal resistance
Symbol
VDD
IOUT
VIN
VOUT
Topr
Tstg
Rth(j-a)
Rating (Note1)
0.3 to 6.0
95
0.3 to VDD + 0.3 (Note2)
0.3 to 17
40 to 85
55 to 150
94 (Note3)
Unit
V
mA
V
V
°C
°C
°C/W
Power dissipation
PD
1.32 (Note3, 4)
W
Note1: Voltage is ground referenced.
Note2: Do not exceed 6.0V.
Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming)
Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each
degree (1°C) that the ambient temperature is exceeded (Ta = 25°C).
Operating Conditions
DC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C)
Characteristics
Symbol
Test Conditions
Min Typ. Max Unit
Supply voltage
VDD
3.0
High level logic input voltage
VIH
Test terminal are SIN,SCK, SLAT , OE
0.7 ×
VDD
L o w l e v e l l o g i c i n p u t v o l t a g e VIL Test terminal are SIN,SCK, SLAT , OE GND
High level SOUT output current
IOH
⎯ ⎯⎯
Low level SOUT output current
Constant current output
IOL
IOUT
Test terminal is OUTn
⎯⎯
1.5
AC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C)
5.5 V
VDD
0.3 ×
VDD
1
1
90
V
V
mA
mA
mA
Characteristics
Symbol
Test
Circuits
Test Conditions
Min Typ. Max Unit
Serial data transfer frequency
fSCK
6
⎯ ⎯ ⎯ 25 MHz
Serial data Hold time
tHOLD1
tHOLD2
6
6
5 ⎯ ⎯ ns
5 ⎯ ⎯ ns
Serial data Setup time
tSETUP1
tSETUP2
6
6
5 ⎯ ⎯ ns
5 ⎯ ⎯ ns
Maximum clock rise time
tr
6 (Note1)
⎯ ⎯ 500 ns
Maximum clock fall time
tf
6 (Note1)
⎯ ⎯ 500 ns
Note1: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock
waveform,it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind
when designing your application.
6 2011-12-14

6 Page









TC62D748CFG pdf, datenblatt
Timing Waveforms
1. SCK, SIN, SOUT
twSCK
SCK
50%
tSETUP1
SIN 50%
50%
50%
twSCK
SOUT
tHOLD1
50%
tpLH/tpHL
50%
2. SCK, SIN, SLAT , OE , OUT0
TC62D748CFG
90%
10%
tr
90%
10%
tf
SCK
50%
50%
SIN
SLAT
OE
tHOLD2
50%
tSETUP2
50%
twSLAT
50%
twOE
50%
OUT0
3. OE , OUT0 to OUT15
tpHL1/tpLH1
50%
tpHL2/tpLH2
twOE
50%
OE
50%
tpHL3
tpLH3
OUT0 to OUT15
90% 50%
10%
tof
50% 90%
10%
tor
12
OFF
ON
2011-12-14

12 Page





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