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PDF ML9042-xx Data sheet ( Hoja de datos )
| Número de pieza | ML9042-xx | |
| Descripción | DOT MATRIX LCD CONTROLLER DRIVER | |
| Fabricantes | LAPIS | |
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LAPIS Semiconductor
ML9042-xx
DOT MATRIX LCD CONTROLLER DRIVER
FEDL9042-01
Issue Date: Nov. 19, 2003
GENERAL DESCRIPTION
The ML9042 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.
FEATURES
Easy interfacing with an 8-bit or 4-bit microcontroller
Switchable between serial and parallel interfaces
Dot-matrix LCD controller driver for a 5 8 dot font
Built-in circuit allowing automatic resetting at power-on
Built-in 17 common signal drivers and 100 segment signal drivers
Two built-in character generator ROMs each capable of generating 240 characters (5 8 dots)
The character generator ROM can be selected by bank switching (ROM1S) pin.
Creation of character patterns by programming: up to 8 character patterns (5 8 dots)
Built-in RC oscillation circuit using external or internal resistors
Program-selectable duties
When ABE bit is “L”: 1/8 duty (1 line: 5 8 dots), or 1/16 duty (2 lines: 5 8 dots)
When ABE bit is “H”: 1/9 duty (1 line: 5 8 dots + arbitrator), or 1/17 duty (2 lines: 5 8 dots + arbitrator)
Cursor display
Built-in bias dividing resistors to drive the LCD
Bi-directional transfer of segment outputs
Bi-directional transfer of common outputs
100-dot arbitrator display
Line display shifting
Built-in voltage multiplier circuit
Gold Bump Chip
ML9042-xx CVWA/DVWA
*xx indicates a character generator ROM code number.
*01, 11 and 21 indicate general character generator ROM code numbers.
CVWA indicates a bump chip with high hardness, and DVWA indicates a bump chip with low
hardness.
1/58
1 page  
LAPIS Semiconductor
FEDL9042-01
ML9042-xx
Symbol
ROM1S
V1 , V2, V3A, V3B, V4
BE
Description
The input pin to switch the ROM bank. “H” selects ROM1 and “L” selects ROM0.
Switching after power-on is prohibited.
The pins to output bias voltages to the LCD.
For 1/4 bias : The V2 and V3B pins are shorted.
For 1/5 bias : The V3A and V3B pins are shorted.
The input pin to enable or disable the voltage multiplier circuit.
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
The voltage multiplier circuit doubles the input voltage between the VIN pin and the
GND pin, and the multiplied voltage referenced to the GND is output to the VOUT pin.
The voltage multiplier circuit can be used only when generating a level higher than the
VDD.
TESTIN
TESTOUT
VIN
V0, VOUT
VC
VCC
T1, T2, T3
VDD
GND
SP
DUMMYVDD
DUMMYGND
DUMMY
The input pin for test circuits. Normally connect this pin to VDD.
The output pin for the test circuits. Normally leave this pin open.
The pin to input voltage to the voltage multiplier.
The pins to supply the LCD drive voltage.
The same potential as the VDD potential is supplied to the VOUT and V0 pins when the
voltage multiplier is not used (BE = “0” or BE = “1”, and the capacitor is not connected
to the VC and VCC pins)
When the voltage multiplier is used (BE = “1”), the multiplied voltage is output to the
VOUT pin, so that the VOUT pin and V0 pin should be connected.
Capacitors for the voltage multiplier should be connected between the GND and the
VOUT pin.
The pin to connect the negative pin of the capacitor for the voltage multiplier. Leave the
pin open when the voltage multiplier circuit is not used.
The pin to connect the positive pin of the capacitor used for the voltage multiplier.
Leave the pin open when the voltage multiplier circuit is not used.
The input pins for test circuits (normally open). Each of these pins is equipped with a
pull-down resistor, so this pin should be left open.
The power supply pin.
The ground level input pin.
The input pin to select the serial or parallel interface.
“L” selects the parallel interface.
“H” selects the serial interface.
The output pin to fix the adjacent input pin to the VDD level. Use this pin only for this
purpose.
The output pin to fix the adjacent input pin to the GND level. Use this pin only for this
purpose.
NC (No Connection) pin.
5/58
5 Page 
LAPIS Semiconductor
FEDL9042-01
ML9042-xx
I/O Characteristics
Parallel Interface Mode
The timing for the input from the CPU and the timing for the output to the CPU are as shown below:
1) WRITE MODE (Timing for input from the CPU)
Parameter
RW/SI, RS0/CSB, RS1 Setup Time
E/SHTB Pulse Width
RW/SI, RS0/CSB, RS1 Hold Time
E/SHTB Rise Time
E/SHTB Fall Time
E/SHTB Pulse Width
E/SHTB Cycle Time
DB0(SO) to DB7 Input Data Setup Time
DB0(SO) to DB7 Input Data Hold Time
Symbol
tB
tW
tA
tr
tf
tL
tC
tI
tH
(VDD = 2.7 to 4.5 V, Ta = –40 to +85C)
Min. Typ. Max. Unit
40 — — ns
450 — — ns
10 — — ns
— — 125 ns
— — 125 ns
430 — — ns
1000
—
—
ns
195 — — ns
10 — — ns
Parameter
RW/SI, RS0/CSB, RS1 Setup Time
E/SHTB Pulse Width
RW/SI, RS0/CSB, RS1 Hold Time
E/SHTB Rise Time
E/SHTB Fall Time
E/SHTB Pulse Width
E/SHTB Cycle Time
DB0(SO) to DB7 Input Data Setup Time
DB0(SO) to DB7 Input Data Hold Time
Symbol
tB
tW
tA
tr
tf
tL
tC
tI
tH
(VDD = 4.5 to 5.5 V, Ta = –40 to +85C)
Min. Typ. Max. Unit
40 — — ns
220 — — ns
10 — — ns
— — 125 ns
— — 125 ns
220 — — ns
500 — — ns
60 — — ns
10 — — ns
RS1, RS0/CSB
VIH
VIL
VIH
VIL
RW/SI
E/SHTB
VIL
tB
tL
VIL
VIL
tr
VIH
DB0(SO) to DB7
tC
tW tf
VIH
tI
VIL
tA
VIL
tH
VIH Input
VIL Data
VIH
VIL
11/58
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML9042-xx.PDF ] | |
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