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PDF ISL26104 Data sheet ( Hoja de datos )
| Número de pieza | ISL26104 | |
| Descripción | Low-Noise 24-bit Delta Sigma ADC | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Low-Noise 24-bit Delta Sigma ADC
ISL26102, ISL26104
The ISL26102 and ISL26104 provide a low-noise
programmable gain amplifier along with a 24-bit Delta-Sigma
Analog-to-Digital Converter with two channel (ISL26102) or
four channel (ISL26104) differential, multiplexed inputs. The
devices feature exceptional noise performance for conversion
rates ranging from 2.5Sps to 4kSps.
The on-chip low-noise programmable-gain amplifier provides
gains ranging from 1 to 128, which supports ±19.5mVFS from
a 5V reference. The high input impedance allows direct
connection of sensors such as load cell bridges to ensure the
specified measurement accuracy without additional circuitry.
The Delta-Sigma ADC features a 3rd-order modulator providing
up to 21.5 bit noise-free performance (10Sps), with
user-selectable word rates. The converter can be operated
from an external clock source, an external crystal (typically
4.9152MHz), or the on-chip oscillator.
The ISL26102 and ISL26104 offer a simple-to-use serial
interface.
The ISL26102 and ISL26104 are available in a Thin Shrink
Small Outline Package (TSSOP). The devices are specified for
operation over the automotive temperature range (-40°C to
+105°C).
Features
• Programmable gain amplifier with gains of 1 to 128
• Low noise: 7nV/√Hz @ PGA = 128
• Linearity error: 0.0002% FS
• Output word rates up to 4kSps
• Low-side switch for load cell power management
• +5V analog and +2.7V to +5V digital supplies
• ISL26102 in 24 Ld TSSOP
• ISL26104 in 28 Ld TSSOP
• ESD 7.5kV - HBM
Applications
• Weigh scales
• Temperature monitors and controls
• Load safety systems
• Industrial process control
• Pressure sensors
Related Literature
AN1704, “Precision Signal Path Data Acquisition System”
AVDD
ON-CHIP
TEMP
SENSOR
CAP
DVDD
DVDD
INTERNAL
CLOCK
EXTERNAL
OSCILLATOR
XTALIN/
CLOCK
XTALOUT
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
ISL26104 AIN3-
ONLY AIN4+
AIN4-
LSPS
INPUT
MULTIPLEXER
PGA
1, 2, 4, 8,16,
32, 64, 128
ΔΣ
ADC
CS
SDO/RDY
SDI
SCLK
PWDN
AGND
CAP DGND DGND VREF+ VREF- DGND DGND
FIGURE 1. BLOCK DIAGRAM
October 12, 2012
FN7608.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL26102, ISL26104
Electrical Specifications VREF+ = 5.0V, VREF- = 0V, AVDD = 5V, DVDD = 5V XTALIN/CLOCK = 4.9152MHz (Note 6)
TA = -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
SYMBOL
PARAMETER
TEST LEVEL OR NOTES
MIN MAX
(Note 7)
TYP
(Note 7)
UNITS
VOLTAGE REFERENCE INPUT
VREF
VREF+
VREF-
VREFI
Voltage Reference Input
Positive Voltage Reference Input
Negative Voltage Reference Input
Voltage Reference Input Current
VREF = VREF+ - VREF-
1.5 5.0 AVDD + 0.1 V
VREF- + 1.5
AVDD + 0.1
V
AGND - 0.1
VREF+ - 1.5
V
350 nA
Low-Side Power Switch
rON ON-resistance
Continuous Current
10 Ω
30 mA
Power Supply Requirements
AVDD
DVDD
AIDD
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Gain of 1
Gain = 2 to 128
4.75
5.0
5.25
V
2.7
5.0
5.25
V
6 10 mA
9 12 mA
Power-down
0.2 2.5 µA
Standby
0.3 µA
DIDD Digital Supply Current
Gain of 1
Gain = 2 to 128
750 950 µA
750 950 µA
Power-down
1 26 µA
Standby
1.8 µA
Power
Normal
Gain = 1
33.75
54.75
Gain = 2 to 128
48.75
64.75
mW
Power-down
6 µW
Standby
10.5
µW
Digital Inputs
VIH
VIL
VOH
VOL
Input Leakage Current
IOH = -1mA
IOL = 1mA
0.7 DVDD
DVDD - 0.4
0.2 DVDD
0.2 DVDD
±10
V
V
V
V
µA
External Clock Input Frequency
0.3 4.9152
MHz
Serial Clock Input Frequency (Note 9)
4 MHz
NOTES:
6. If the device is driven with an external clock, best performance will be achieved if the rise and fall times of the clock are slowed to less than 20ns
(10% to 90% rise/fall time).
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Output word rates (MIN and MAX in the table) are specified using 4.9152MHz clock. If a different clock frequency is used, or if the internal oscillator
is used as the clock source for the converter, the output word rates will scale proportionally to the change in the clock frequency.
9. The OWR (Output Word Rate) setting dictates the rate at which the SDO/RDY signal will fall. To read every conversion word, reading of the conversion
word should begin immediately after SDO/RDY falls and the SCLK rate should be fast enough to read all 24 data bits of the conversion word before
the next falling edge of SDO/RDY that indicates that a new conversion word is available.
5 FN7608.0
October 12, 2012
5 Page 
ISL26102, ISL26104
case, there is no difference in power consumption for standby or
power-down modes.
The Output Word Rate register allows the user to set the rate at
which the converter performs conversions. Table 3 lists the
output word rate options.
The Input Mux Selection register defines the input signal that will
be used when conversions are performed. The signals include
either 2 (ISL26102) or 4 (ISL26104) differential input channels,
an on-chip temperature sensor, or the monitor node for the AVDD
supply voltage. Note that if the temperature sensor or the AVDD
monitor are selected the PGA gain is internally set for 1x gain.
The PGA Gain register allows the user to set the PGA gain setting
for the channel pointed to by the Channel Pointer register. The
PGA provides gain settings of 1x (in this gain setting the
programmable gain amplifier is actually bypassed and the signal
goes directly to the modulator), 2x, 4x, 8x, 16x, 32x, 64x, and
128x.
The Conversion Control register provides the means to initiate
offset calibration, or initiate single or continuous conversions. If
bit b2 of this register is set to a logic 1, an offset calibration will
be performed and the states of bits b1 and b0 are ignored. The
state of bit b2 will be set back to a logic 0 after the offset
calibration is complete.
If the b1b0 bits are set to 01, a single conversion will be
performed. When the conversion is completed, the bits will be set
back to 00, the SDO/RDY pin will be taken low (note that the CS
pin must be a logic 1 for SDO/RDY to fall) and the conversion
data will be held in a register. If the user enables CS (held at
logic 1) and provides 24 SCLKs to the SCLK pin, the data word
will be shifted out of the SDO/RDY pin as a 24-bit two’s
complement word, starting with the MSB. Data bits are clocked
out on the rising edge of SCLK. If the entire 24-bit data word is
not read before the completion of the next conversion, it will be
overwritten with the new conversion word.
If the b1b0 bits are set to 10, conversions will be performed
continuously until bits b1b0 are set to either 00 or 01, Standby
mode is activated, or the PDWN pin is taken low. Refer to
“Reading Conversion Data” on page 14.
The Delay Timer register allows the user to program a delay time,
which will be inserted between the time that the user selects an
input to be converted via the Input Mux Selection register and
when the conversion is started. If continuous conversions are
selected via the Conversion Control register, the Input Mux
Selection register can be changed without needing to stop
conversions. The Delay Timer register allows the user to insert a
delay between when the mux is changed and when a new
conversion is started. If the Delay Timer register is set to all 0's
the minimum delay will be 100µs.
Any time the PGA Gain setting is changed, the channel selection
is changed, or a command is given to start conversion(s), the
user can expect a delay before the SDO/RDY signal will fall. This
delay is defined by Equation 1:
[4ms + (Delay Timer Register Setting∗4ms) + 100μs ) + 4∗(1 ⁄ OWR)]
(EQ. 1)
The first 4ms is for the PGA to settle. This delay cannot be
changed. The Delay Timer register setting is user controllable,
and it dictates the majority of the second section of the equation.
The 4*(1/OWR) term is the time required for the filter to settle at
the OWR (Output Word Rate), which has been selected in the
Output Word Rate register.
The PGA Offset Array registers hold the calibration results for the
offset calibration done for each of the PGA gain settings. The
result of an offset calibration is a 24-bit twos complement word.
There are eight high byte registers, eight mid byte registers and
eight low byte registers. When reading or writing to one of the
PGA Offset Array byte registers, the register selected will be
determined by the PGA Pointer Register.
The PGA Pointer register contains the pointer to the PGA Offset
register array bytes associated with a specific PGA gain.
11 FN7608.0
October 12, 2012
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ISL26104.PDF ] | |
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