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Teilenummer | ISL23318 |
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Beschreibung | 128-taps Low Voltage Digitally Controlled Potentiometer | |
Hersteller | Intersil | |
Logo | ||
Gesamt 19 Seiten Single, 128-taps Low Voltage Digitally Controlled
Potentiometer (XDCP™)
ISL23318
The ISL23318 is a volatile, low voltage, low noise, low power,
I2C Bus™, 128 Taps, single digitally controlled potentiometer
(DCP), which integrates DCP core, wiper switches and control
logic on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) that can be directly written to and
read by the user. The contents of the WR controls the position
of the wiper. When powered on, the ISL23318’s wiper will
always commence at mid-scale (64 tap position).
The low voltage, low power consumption, and small package
of the ISL23318 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23318 has a VLOGIC
pin allowing down to 1.2V bus operation, independent from the
VCC value. This allows for low logic levels to be connected
directly to the ISL23318 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
Features
• 128 resistor taps
• I2C serial interface
- No additional level translator for low bus supply
- Two address pins allow up to four devices per bus
• Power supply
- VCC = 1.7V to 5.5V analog power supply
- VLOGIC = 1.2V to 5.5V I2C bus/logic power supply
• Wiper resistance: 70Ω typical @ VCC = 3.3V
• Shutdown Mode - forces the DCP into an end-to-end open
circuit and RW is shorted to RL internally
• Power-on preset to mid-scale (64 tap position)
• Shutdown and standby current <2.8µA max
• DCP terminal voltage from 0V to VCC
• 10kΩ, 50kΩ or 100kΩ total resistance
• Extended industrial temperature range: -40°C to +125°C
• 10 Ld MSOP or 10 Ld UTQFN packages
• Pb-free (RoHS compliant)
Applications
• Gain adjustment in battery powered instruments
• Trimming sensor circuits
• Power supply margining
• RF power amplifier bias compensation
10000
8000
6000
4000
2000
0
0 32 64 96 128
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10k DCP
VREF
RH
ISL23318
RW
RL
-
+
ISL28114
VREF_M
FIGURE 2. VREF ADJUSTMENT
July 26, 2011
FN7887.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners
ISL23318
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
TCR Resistance Temperature Coefficient
(Note 19)
W option; Wiper register set between
19 hex and 7F hex
220 ppm/°C
U option; Wiper register set between 19
hex and 7F hex
100
ppm/°C
T option; Wiper register set between 19
hex and 7F hex
75
ppm/°C
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
ILOGIC VLOGIC Supply Current (Write/Read)
VLOGIC = 5.5V,
fSCL = 400kHz
VCC
(for
= 5.5V,
I2C active
read
and
write)
200 µA
VLOGIC = 1.2V,
fSCL = 400kHz
VCC
(for
= 1.7V,
I2C active
read
and
write)
5 µA
ICC VCC Supply Current (Write/Read)
ILOGIC SB VLOGIC Standby Current
VLOGIC = 5.5V, VCC = 5.5V
VLOGIC = 1.2V, VCC = 1.7V
IV2LCOGinICte=rfaVcCeC
=
in
5.5V,
standby
18 µA
10 µA
1.3 µA
IV2LCOGinICte=rfa1c.2eVi,nVsCtCan=d1by.7V,
0.4 µA
ICC SB VCC Standby Current
IV2LCOGinICte=rfaVcCeC
=
in
5.5V,
standby
1.5 µA
IV2LCOGinICte=rfa1c.2eVi,nVsCtCan=d1by.7V,
1 µA
ILOGIC SHDN VLOGIC Shutdown Current
IV2LCOGinICte=rfaVcCeC
=
in
5.5V,
standby
1.3 µA
IV2LCOGinICte=rfa1c.2eVi,nVsCtCan=d1by.7V,
0.4 µA
ICC SHDN VCC Shutdown Current
IV2LCOGinICte=rfaVcCeC
=
in
5.5V,
standby
1.5 µA
IV2LCOGinICte=rfa1c.2eVi,nVsCtCan=d1by.7V,
1 µA
ILkgDig
tDCP
Leakage Current, at Pins A0, A1, SDA, SCL Voltage at pin from GND to VLOGIC
Wiper Response Time
SCL rising edge of the acknowledge bit
after data byte to wiper new position
-0.4
<0.1
1.5
0.4
µA
µs
tShdnRec DCP Recall Time from Shutdown Mode
SCL rising edge of the acknowledge bit
after ACR data byte to wiper recalled
position and RH connection
1.5
µs
VCC, VLOGIC VCC ,VLOGIC Ramp Rate
Ramp
(Note 21)
Ramp monotonic at any level
0.01
50 V/ms
6 FN7887.0
July 26, 2011
6 Page ISL23318
Typical Performance Curves (Continued)
20
150
140
15
130
10
120
5 110
0
16 32 48 64 80 96 112 128
TAP POSITION (DECIMAL)
FIGURE 17. 100k TCv vs TAP POSITION
10016
32 48 64 80 96 112
TAP POSITION (DECIMAL)
FIGURE 18. 100k TCr vs TAP POSITION
128
SCL CLOCK
1V/DIV
RW PIN
10mV/DIV
1µs/DIV
FIGURE 19. WIPER DIGITAL FEED-THROUGH
1V/DIV
1µs/DIV
WIPER
20mV/DIV
5µs/DIV
FIGURE 20. WIPER TRANSITION GLITCH
1V/DIV
0.1s/DIV
VRH = VCC
SCL 9TH CLOCK OF THE
DATA BYTE (ACK)
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
12
VRW
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
FN7887.0
July 26, 2011
12 Page | ||
Seiten | Gesamt 19 Seiten | |
PDF Download | [ ISL23318 Schematic.PDF ] |
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