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ISL22512 Schematic ( PDF Datasheet ) - Intersil

Teilenummer ISL22512
Beschreibung Single Push Button Controlled Potentiometer
Hersteller Intersil
Logo Intersil Logo 




Gesamt 12 Seiten
ISL22512 Datasheet, Funktion
ISL22512
Single Push Button Controlled Potentiometer (XDCP™)
Data Sheet
October 12, 2015
FN6679.3
Low Noise, Low Power, 16 Taps, Push
Button Controlled Potentiometer
The Intersil ISL22512 is a three-terminal digitally-controlled
potentiometer (XDCP) implemented by a resistor array
composed of 15 resistive elements and a wiper switching
network. The ISL22512 features a push button control, a
shutdown mode, as well as an industry-leading µTQFN
package.
The push button control has individual PU and PD inputs for
adjusting the wiper. To eliminate redundancy, the wiper
position will automatically increment or decrement if one of
these inputs is held longer than one second.
Forcing both PU and PD low for more than two seconds
activates shutdown mode. Shutdown mode disconnects the
top of the resistor chain and moves the wiper to the lowest
position, minimizing power consumption.
The three terminals accessing the resistor chain naturally
configure the ISL22512 as a voltage divider. A rheostat is
easily formed by floating an end terminal or connecting it to
the wiper.
NC
VCC (SUPPLY VOLTAGE)
O
PU 1
9 VCC
PD 2 µTQFN 8 ASE
RH 3 (Top View) 7 RL
PU
RH VSS 4
6 RW
PD CBOLNOTCRKOL RW
NC
ASE
O
PU 1
8 VCC
RL PD 2 SOIC 7 ASE
RH 3 (Top View) 6 RL
VSS 4
5 RW
VSS (GROUND)
Features
• Solid-State Non-Volatile Potentiometer
• Push Button Controlled
• Single or Auto Increment/Decrement
- Fast Mode after 1s Button Press
• AUTOSTORE of Last Wiper Position or Manual Store of
Wiper Position
• Shutdown Mode
• 16 Wiper Tap Points
- Middle Scale Wiper Position on Power-Up
• Low Power CMOS
- VCC = 2.7V to 5.5V
- Terminal Voltage, 0 to VCC
- Standby Current, 3µA max
• RTOTAL Value = 10k
• High Reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T +55°C
• Packages
- 8 Ld SOIC
- 10 Ld µTQFN (2.1mmx1.6mm)
• Pb-Free (RoHS Compliant)
Applications
• Volume Control
• LED/LCD Brightness Control
• Contrast Control
• Programming Bias Voltages
• Ladder Networks
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2008, 2009, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






ISL22512 Datasheet, Funktion
Slow Mode Timing
tDB
PU
ISL22512
tGAP
MI*
VW
*MI in the AC timing diagram refers to the minimum incremental change in the wiper voltage.
Fast Mode Timing
PU
tDB
tS FAST
tS SLOW
VW MI*
1s
*MI in the AC timing diagram refers to the minimum incremental change in the wiper voltage.
Shutdown Mode Timing
PU
tDB
2s
SHUTDOWN MODE
PD
VW
AUTOSTORE Mode Timing
tDB
PU
250ms
PD
(HIGH)
ASE
(LOW)
WIPER
POSITION
N
N+1
6
2s 20ms
MEMORY WRITE
CYCLE
N+2
FN6679.3
October 12, 2015

6 Page









ISL22512 pdf, datenblatt
ISL22512
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
N
2X 0.10 C
1
2X 0.10 C
2
TOP VIEW
AB
E
0.10 C
0.05 C
A
SEATING PLANE
A1
SIDE VIEW
C
(DATUM A)
PIN #1 ID
12
NX L
4xk
N
N-1
e
3
(ND-1) X e
(DATUM B)
NX b 5
0.10 M C A B
0.05 M C
BOTTOM VIEW
NX (b)
5
(A1)
SECTION "C-C"
CL
L
e
CC
TERMINAL TIP
FOR ODD TERMINAL/SIDE
b
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
SYMBOL
MIN NOMINAL MAX
NOTES
A 0.45 0.50 0.55
-
A1
-
- 0.05
-
A3 0.127 REF -
b 0.15 0.20 0.25
5
D 2.05 2.10 2.15
-
E 1.55 1.60 1.65
-
e
0.50 BSC
-
k 0.20 - - -
L 0.35 0.40 0.45
-
N 10 2
Nd 4 3
Ne 1 3
0 - 12 4
NOTES:
Rev. 3 6/06
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.05 MIN
2.50
1.75
L
0.275
2.00
0.80
0.10 MIN
DETAIL “A” PIN 1 ID
0.25
0.50
LAND PATTERN 10
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12 FN6679.3
October 12, 2015

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