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5P49V5935 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 5P49V5935
Beschreibung Programmable Clock Generator
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 30 Seiten
5P49V5935 Datasheet, Funktion
Programmable Clock Generator
5P49V5935
DATASHEET
Description
The 5P49V5935 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The 5P49V5935 by default uses an integrated 25MHz crystal
as input reference. It also has a redundant external clock
input. A glitchless manual switchover functions allows
selection of either one as mentioned above as input reference
during normal operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
NC
NC
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2 17
3 16
4
EPAD
15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
Features
Generates up to four independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Four fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
Input frequency ranges:
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
24-pin VFQFPN
5P49V5935 NOVEMBER 11, 2016
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©2015 Integrated Device Technology, Inc.






5P49V5935 Datasheet, Funktion
5P49V5935 DATASHEET
Output Skew
For outputs that share a common output divide value, there
will be the ability to skew outputs by quadrature values to
minimize interaction on the PCB. The skew on each output
can be adjusted from 0 to 360 degrees. Skew is adjusted in
units equal to 1/32 of the VCO period. So, for 100 MHz output
and a 2800 MHz VCO, you can select how many 11.161pS
units you want added to your skew (resulting in units of 0.402
degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so
on. The granularity of the skew adjustment is always
dependent on the VCO period and the output period.
Output Drivers
The OUT1 to OUT4 clock outputs are provided with
register-controlled output drivers. By selecting the output drive
type in the appropriate register, any of these outputs can
support LVCMOS, LVPECL, HCSL or LVDS logic levels
The operating voltage ranges of each output is determined by
its independent output power pin (VDDO) and thus each can
have different output voltage levels. Output voltage levels of
2.5V or 3.3V are supported for differential HCSL, LVPECL
operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS
and differential LVDS operation.
Each output may be enabled or disabled by register bits.
When disabled an output will be in a logic 0 state as
determined by the programming bit table shown on page 6.
LVCMOS Operation
When a given output is configured to provide LVCMOS levels,
then both the OUTx and OUTxB outputs will toggle at the
selected output frequency. All the previously described
configuration and control apply equally to both outputs.
Frequency, phase alignment, voltage levels and enable /
disable status apply to both the OUTx and OUTxB pins. The
OUTx and OUTxB outputs can be selected to be
phase-aligned with each other or inverted relative to one
another by register programming bits. Selection of
phase-alignment may have negative effects on the phase
noise performance of any part of the device due to increased
simultaneous switching noise within the device.
Device Hardware Configuration
The 5P49V5935 supports an internal One-Time
Programmable (OTP) memory that can be pre-programmed
at the factory with up to 4 complete device configuration.
These configurations can be over-written using the serial
interface once reset is complete. Any configuration written via
the programming interface needs to be re-written after any
power cycle or reset. Please contact IDT if a specific
factory-programmed configuration is desired.
Device Start-up & Reset Behavior
The 5P49V5935 has an internal power-up reset (POR) circuit.
The POR circuit will remain active for a maximum of 10ms
after device power-up.
Upon internal POR circuit expiring, the device will exit reset
and begin self-configuration.
The device will load internal registers according to Table 3.
Once the full configuration has been loaded, the device will
respond to accesses on the serial port and will attempt to lock
the PLL to the selected source and begin operation.
Power Up Ramp Sequence
VDDA and VDDD must ramp up together. VDDO0~4 must
ramp up before, or concurrently with, VDDA and VDDD. All
power supply pins must be connected to a power rail even if
the output is unused. All power supplies must ramp in a linear
fashion and ramp monotonically.
VDDO0~4
VDDA
VDDD
PROGRAMMABLE CLOCK GENERATOR
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NOVEMBER 11, 2016

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5P49V5935 pdf, datenblatt
5P49V5935 DATASHEET
Table 15:DC Electrical Characteristics for 1.8V LVCMOS (VDDO = 1.8V±5%, TA = -40°C to +85°C)
Symbol Parameter
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = -8mA
0.7 xVDDO
VDDO
V
VOL
Output LOW Voltage
IOL = 8mA
0.25 x VDDO V
IOZDD Output Leakage Current (OUT1~4) Tri-state outputs, VDDO = 3.465V
5 µA
IOZDD Output Leakage Current (OUT0) Tri-state outputs, VDDO = 3.465V
30 µA
VIH Input HIGH Voltage
Single-ended inputs - CLKSEL, SD/OE 0.7 * VDDD
VDDD + 0.3 V
VIL Input LOW Voltage
Single-ended inputs - CLKSEL, SD/OE GND - 0.3
0.3 * VDDD V
VIH Input HIGH Voltage
Single-ended input OUT0_SEL_I2CB
0.65 * VDDO0
VDDO0 + 0.3 V
VIL Input LOW Voltage
Single-ended input OUT0_SEL_I2CB
GND - 0.3
0.4 V
CLKSEL, SD/OE, SEL1/SDA,
TR/TF
Input Rise/Fall Time
SEL0/SCL
300 nS
Table 16:DC Electrical Characteristics for LVDS(VDDO = 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)
Symbol
Parameter
VOT (+)
VOT (-)
VOT
VOS
VOS
IOS
IOSD
Differential Output Voltage for the TRUE binary state
Differential Output Voltage for the FALSE binary state
Change in VOT between Complimentary Output States
Output Common Mode Voltage (Offset Voltage)
Change in VOS between Complimentary Output States
Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDDO
Differential Outputs Short Circuit Current, VOUT+ = VOUT -
Min Typ Max Unit
247 454 mV
-247
-454
mV
50 mV
1.125
1.25
1.375
V
50 mV
9 24 mA
6 12 mA
Table 17:DC Electrical Characteristics for LVDS (VDDO = 1.8V+5%, TA = -40°C to +85°C)
Symbol
Parameter
VOT (+)
VOT (-)
VOT
VOS
VOS
IOS
IOSD
Differential Output Voltage for the TRUE binary state
Differential Output Voltage for the FALSE binary state
Change in VOT between Complimentary Output States
Output Common Mode Voltage (Offset Voltage)
Change in VOS between Complimentary Output States
Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDDO
Differential Outputs Short Circuit Current, VOUT+ = VOUT -
Min
247
-247
0.8
Typ
0.875
9
6
Max
454
-454
50
0.95
50
24
12
Unit
mV
mV
mV
V
mV
mA
mA
Table 18:DC Electrical Characteristics for LVPECL (VDDO = 3.3V+5% or 2.5V+5%, TA = -40°C to
+85°C)
Symbol
Parameter
VOH
VOL
VSWING
Output Voltage HIGH, terminated through 50tied to VDD - 2 V
Output Voltage LOW, terminated through 50tied to VDD - 2 V
Peak-to-Peak Output Voltage Swing
Min Typ Max Unit
VDDO - 1.19
VDDO - 1.94
0.55
VDDO - 0.69
VDDO - 1.4
0.993
V
V
V
PROGRAMMABLE CLOCK GENERATOR
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NOVEMBER 11, 2016

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