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5P49V5929 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 5P49V5929
Beschreibung Programmable Clock Generator
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 27 Seiten
5P49V5929 Datasheet, Funktion
Programmable Clock Generator
5P49V5929
DATASHEET
Description
The 5P49V5929 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2 17
3
EPAD
16
4
GND
15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT3
OUT4
VDDO3
OUT5
OUT6
Features
Generates up to four independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs
Four fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
Nine LVCMOS outputs, including one reference output
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
24-pin VFQFPN
5P49V5929 NOVEMBER 11, 2016
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©2016 Integrated Device Technology, Inc.






5P49V5929 Datasheet, Funktion
5P49V5929 DATASHEET
Reference Clock Input Pins and
Selection
The 5P49V5929 supports up to two clock inputs. One input
supports a crystal between XIN and XOUT. XIN can also be
driven from a single ended reference clock. XIN can accept
small amplitude signals like from TCXO or one channel of a
differential clock.
The second clock input (CLKIN, CLKINB) is a fully differential
input that only accepts a reference clock. The differential input
accepts differential clocks from all the differential logic types
and can also be driven from a single ended clock on one of the
input pins.
The CLKSEL pin selects the input clock between either
XTAL/REF or (CLKIN, CLKINB).
Either clock input can be set as the primary clock. The primary
clock designation is to establish which is the main reference
clock to the PLL. The non-primary clock is designated as the
secondary clock in case the primary clock goes absent and a
backup is needed. See the previous page for more details
about primary versus secondary clock operation.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits must be set to “0x” for
manual switchover which is detailed in Manual Switchover
Mode section.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
XTAL[5:0] Tuning Capacitor Characteristics
Parameter
XTAL
Bits Step (pF) Min (pF)
6 0.5
9
Max (pF)
25
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
You can write the following equation for this capacitance:
Ci = 9pF + 0.5pF × XTAL[5:0]
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
 
You can write the following equations for the total capacitance
at each crystal pin:
CXIN = Ci1 + Cs1 + Ce1
CXOUT = Ci2 + Cs2 + Ce2
Ci1 and Ci2 are the internal, tunable capacitors. Cs1 and Cs2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
Ce1 and Ce2 are additional external capacitors that can be
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce1 and/or Ce2 to avoid
crystal startup issues. Ce1 and Ce2 can also be used to adjust
for unpredictable stray capacitance in the PCB.
The final load capacitance of the crystal:
CL = CXIN × CXOUT / (CXIN + CXOUT)
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
CXIN = CXOUT = Cx CL = Cx / 2
The complete formula when the capacitance at both crystal
pins is the same:
CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
PROGRAMMABLE CLOCK GENERATOR
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NOVEMBER 11, 2016

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5P49V5929 pdf, datenblatt
5P49V5929 DATASHEET
Table 8: Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5P49V5929. These ratings, which are standard values for IDT
commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect
product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDDA, VDDD, VDDO
Inputs
XIN/REF
CLKIN, CLKINB
Other inputs
Outputs, VDDO (LVCMOS)
Outputs, IO (SDA)
Package Thermal Impedance, JA
Package Thermal Impedance, JC
Storage Temperature, TSTG
ESD Human Body Model
Junction Temperature
Rating
3.465V
0V to 1.2V voltage swing
0V to 1.2V voltage swing single-ended
-0.5V to VDDD
-0.5V to VDDO+ 0.5V
10mA
42C/W (0 mps)
41.8C/W (0 mps)
-65C to 150C
2000V
125°C
Table 9: Recommended Operation Conditions
Symbol
Parameter
VDDOX
VDDOX
VDDOX
VDDD
VDDA
Power supply voltage for supporting 1.8V outputs
Power supply voltage for supporting 2.5V outputs
Power supply voltage for supporting 3.3V outputs
Power supply voltage for core logic functions
Analog power supply voltage. Use filtered analog power
supply.
TA
CLOAD_OUT
FIN
Operating temperature, ambient
Maximum load capacitance (3.3V LVCMOS only)
External reference crystal
External reference clock CLKIN, CLKINB
tPU Power up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
Min
1.71
2.375
3.135
1.71
1.71
-40
1
1
0.05
Typ Max Unit
1.8
1.89
V
2.5
2.625
V
3.3
3.465
V
3.465
V
3.465
V
+85 °C
15 pF
40 MHz
200
5 ms
Note: VDDO1, VDDO2, VDDO3, and VDDO4 must be powered on either before or simultaneously with VDDD, VDDA and VDDO0.
PROGRAMMABLE CLOCK GENERATOR
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