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LE25S20MB Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer LE25S20MB
Beschreibung 2M-bit (256K x 8) Serial Flash Memory
Hersteller ON Semiconductor
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Gesamt 22 Seiten
LE25S20MB Datasheet, Funktion
LE25S20MB
Advance Information
CMOS LSI
2M-bit (256K x 8)
Serial Flash Memory
Overview
The LE25S20MB is a SPI bus flash memory device with a 2M bit (256K
8-bit) configuration. It uses a single 1.8V power supply. While making the
most of the features inherent to a serial flash memory device, the
LE25S20MB is housed in an 8-pin ultra-miniature package. All these
features make this device ideally suited to storing program in applications
such as portable information devices, which are required to have increasingly
more compact dimensions. The LE25S20MB also has a small sector erase
capability which makes the device ideal for storing parameters or data that
have fewer rewrite cycles and conventional EEPROMs cannot handle due to
insufficient capacity.
Features
Read/write operations enabled by single 1.8V power supply :
1.65 to 1.95V supply voltage range
Operating frequency : 40MHz
Temperature range
: 40 to 85C
Serial interface
: SPI mode 0, mode 3 supported
Sector size
: 4K bytes/small sector, 64K bytes/sector
Small sector erase, sector erase, chip erase functions
Page program function (256 bytes/page)
Block protect function
Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40ms (typ), 150ms (max)
Sector erase time
: 80ms (typ), 250ms (max)
Chip erase time
: 300ms (typ), 3.0s (max)
Page program time : 3.0ms/256 bytes (typ), 3.5ms/256 bytes (max)
Status functions
: Ready/busy information, protect information
Data retention period : 20 years
Package
: SOP8K (200mil)
www.onsemi.com
SOP8K (200mil)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 22 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
October 2014 - Rev. P0
1
Publication Order Number :
LE25S20MB/D






LE25S20MB Datasheet, Funktion
LE25S20MB
Description of Commands and Their Operations
A detailed description of the functions and operations corresponding to each command is presented below.
1. Standard SPI read
There are two read commands, the standard SPI read command and High-speed read command.
1-1. Read command
Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses
following (03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference.
"Figure 4-a Read" shows the timing waveforms.
Figure 4-a Read
CS
SCK
SI
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47
8CLK
03h
Add. Add. Add.
SO
1-2. High-speed Read command
High Impedance
N N+1 N+2
DATA DATA DATA
MSB MSB MSB
Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8
dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a
reference. "Figure 4-b High-speed Read" shows the timing waveforms.
Figure 4-b High-speed Read
CS
SCK
SI
SO
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55
8CLK
MSB
0Bh
Add. Add. Add.
High Impedance
X
N N+1 N+2
DATA DATA DATA
MSB MSB MSB
When SCK is input continuously after the read command has been input and the data in the designated addresses
has been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the
highest address (3FFFFh), the internal address returns to the lowest address (00000h), and data output is continued.
By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is
deselected, the output pin SO is in a high-impedance state.
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LE25S20MB pdf, datenblatt
LE25S20MB
8. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 13 Chip Erase" shows the
timing waveforms, and Figure 20 shows a chip erase flowchart. The chip erase command consists only of the first
bus cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase
operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer.
Erase end can also be detected using status register RDY.
Figure 13 Chip Erase
CS
Self-timed
Erase Cycle
tCHE
SCK
SI
SO
Mode3
Mode0
01234567
8CLK
60h / C7h
MSB
High Impedance
9. Page Program
Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page
(page addresses: A17 to A8). Before initiating page program, the data on the page concerned must be erased using
small sector erase, sector erase, or chip erase. "Figure 14 Page Program" shows the page program timing
waveforms, and Figure 21 shows a page program flowchart. After the falling CS, edge, the command (02H) is
input followed by the 24-bit addresses. Addresses A17 to A0 are valid. The program data is then loaded at each
rising clock edge until the rising CS edge, and data loading is continued until the rising CS edge. If the data loaded
has exceeded 256 bytes, the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte
increments, and the program operation is not performed at the rising CS edge occurring at any other timing.
Figure 14 Page Program
CS
Self-timed
Program Cycle
tPP
SCK
SI
SO
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47
8CLK
MSB
02h
Add. Add. Add. PD
PD
High Impedance
2079
PD
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