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PDF KL7107 Data sheet ( Hoja de datos )
| Número de pieza | KL7107 | |
| Descripción | Digit LED Display / A/D Converters | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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3 ½ - Digit LED Display, A/D Converters
TECHNICAL DATA
KL7107
DESCRIPTION
The KL7107 are high performance, low power, 3 ½
digit A/D converters. Included are seven segment decoders,
display drivers, a reference, and a clock.
The KL7107 will directly drive an instrument size light
emitting diode (LED) display.
The KL7107 bring together a combination of high
accuracy,versatility, and true economy. It features autozero
to less than 10 µV, zero drift of less than 1µV/°C, input
bias current of 10pA (Max), and rollover error of less than
one count. True differential inputs and reference are useful
in all systems, but give the designer an uncommon
advantage when measuring load cells, strain gauges and
other bridge type transducers.
40
1
DIP-40
Device
KL7107N
ORDERING INFORMATION
Temperature Range
ТA= 0°C …+70°C
Package
DIP-40
Packing
Tube
FEATURES
• Guaranteed Zero Reading for 0V Input on All Scales
• True Polarity at Zero for Precise Null Detection
• 1pA Typical Input Current
• True Differential Input and Reference,
Direct LED Display Drive
• Low Noise – Less Than 15µVp-p
• On Chip Clock and Reference
• Low Power Dissipation – Typically Less Than 10mW
• No Additional Active Circuits Required
• Enhanced Display Stability
PIN CONNECTIONS
TOP VIEW
V+ 1
D1 2
C1 3
B1 4
A1 5
F1 6
G1 7
E1 8
D2 9
С2 10
B2 11
A2 12
F2 13
E2 14
D3 15
B3 16
F3 17
E3 18
(1000) AB4 19
POL 20
(MINUS)
40 OSC 1
39 OSC 2
38 OSC 3
37 TEST
36 REF H1
35 REF L0
34 CREF+
33 CREF-
32 COMMON
31 IN HI
30 IN LO
29 A-Z
28 BUFF
27 INT
26 V-
25 G2 (10,s)
24 C3
23 A3
22 G3
(100 , s)
21 GND
1 July 2011, ver.00
1 page  
KL7107
Detailed Description
Analog Section
Figure 2 shows the Analog Section. Each measurement cycle is
divided into three phases. They are (1) auto-zero (A-Z), (2) signal
integrate (INT) and (3) de-integrate (DE).
proportional to the input signal. Specifically the digital reading
displayed is:
DISPLAY COUNT = 1000 ( VIN )
VREF
Auto-Zero Phase
During auto-zero three things happen. First, input high and low are
disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor СAZ to compensate for
offset voltages in the buffer amplifier, integrator, and comparator.
Since the comparator is included in the loop, the A-Z accuracy is
limited only by the noise of the system. In any case, the offset
referred to the input is less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the internal
short is removed, and the internal input high and low are connected
to the external pins. The converter then integrates the differential
voltage between IN HI and IN LO for a fixed time. This differential
voltage can be within a wide common mode range: up to 1V from
either supply. If, on the other hand, the input signal has no return
with respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common mode voltage.
At the end of this phase, the polarity of the integrated signal is
determined.
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input low is
internally connected to analog COMMON and input high is
connected across the previously charged reference capacitor.
Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator output
to return to zero. The time required for the output to return to zero
is
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
0.5V below the positive supply to 1V above the negative supply. In
this range, the system has a CMRR of 86dB typical. However, care
must be exercised to assure the integrator output does not saturate.
A worst case condition would be a large positive common mode
voltage with a near full scale negative differential input voltage.
The negative input signal drives the integrator positive when most of
its swing has been used up by the positive common mode voltage.
For these critical applications the integrator output swing can be
reduced to less than the recommended 2V full scale swing with
little loss of accuracy. The integrator output can swing to within
0.3V of either supply without loss of linearity.
Differential Reference
The reference voltage can be generated anywhere within the power
supply voltage of the converter. The main source of common mode
error is a roll-over voltage caused by the reference capacitor losing
or gaining charge to stray capacity on its nodes. If there is a large
common mode voltage, the reference capacitor can gain charge
(increase voltage) when called up to de-integrate a positive signal
but lose charge (decrease voltage) when called up to de-integrate a
negative input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough in
comparison to the stray capacitance, this error can be held to less than
0.5 count worst case. (See Component Value Selection.)
FIGURE 2. ANALOG SECTION
5
July 2011, ver.00
5 Page 
PAKAGE DIMENSION
40-Pin Plastic Dual-in-Line
KL7107
Dimension, mm
A max 6.35
Aı min 0.38
min 3.18
A2 max 4.95
min 0.36
B
max 0.56
min 0.77
B2 max 1.78
min 0.20
C
max 0.38
min 50.30
D
max 53.20
min 15.24
E
max 15.87
min 12.32
E1 max 14.73
e nom 2.54
e2 nom 15.24
min 2.92
L
max 5.08
α min 0º
max 10º
11 July 2011, ver.00
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet KL7107.PDF ] | |
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