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64F2646 Schematic ( PDF Datasheet ) - Renesas

Teilenummer 64F2646
Beschreibung HD64F2646
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
64F2646 Datasheet, Funktion
Hitachi 16-Bit Single-Chip Microcomputer
H8S/2646 Series
H8S/2646
HD6432646
H8S/2645
HD6432645
H8S/2647
HD6432647
H8S/2648
HD6432648
H8S/2646R F-ZTAT™
HD64F2646R
H8S/2648R F-ZTAT™
HD64F2648R
Hardware Manual
ADE-602-207C
Rev. 4.0
9/20/02
Hitachi, Ltd.
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.






64F2646 Datasheet, Funktion
H8S/2646 Series manuals:
Manual Title
H8S/2646 Series Hardware Manual
H8S/2600 Series, H8S/2000 Series Programming Manual
ADE No.
This manual
ADE-602-083
Users manuals for development tools:
Manual Title
C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual
Simulator Debugger (for Windows) Users Manual
Hitachi Embedded Workshop Users Manual
ADE No.
ADE-702-247
ADE-702-037
ADE-702-201
Application Notes:
Manual Title
H8S Series Technical Q & A
ADE No.
ADE-502-059

6 Page









64F2646 pdf, datenblatt
Section
23.1 Absolute
Maximum Ratings
Table 23-1
Absolute Maximum
Ratings
Page
753
Description
Input voltage (OSC1, OSC2)
Vin
lnput voltage (XTAL, EXTAL)
Vin
Input voltage (ports 4 and 9)
Vin
Input voltage (ports A, B, C, D, E, Vin
ports PF2, PF4 to PF6)
Input voltage (ports H and J)
Vin
Input voltage (except ports 4, 9, A, Vin
B, C, D, E, ports PF2, PF4 to PF6,
H and J)
0.3 +3.5
0.3 to ACC +0.3
0.3 to AVCC +0.3
0.3 to LPVCC +0.3
0.3 to PWMVCC +0.3
0.3 to VCC +0.3
V
V
V
V
V
V
23.3 DC
Characteristics
Table 23-2 DC
Characteristics
755,
758
23.4.1 Clock Timing 761
Table 23-4 Clock
Timing
B.1 Address
858
Input high
voltage
RES, STBY,
NMI, FWE,
MD2 to MD0
VIH
VCC 0.7
VCC + 0.3 V
Input low
voltage
EXTAL
Ports 1 to 3, 5,
H, J, K
Ports PF0, PF3,
PF7
HRxD
Ports A to E,
Ports PF2, PF4
to PF6
Ports 4, 9
RES, STBY,
NMI, FWE,
MD2 to MD0
VIL
EXTAL
Ports 1 to 3, 5,
A to F, H, J, K
HRxD
VCC × 0.7
2.2
VCC + 0.3
VCC + 0.3
2.2 VCC + 0.3
2.2 LPVCC + 0.3
AVCC × 0.7
0.3
AVCC + 0.3
0.5 V
0.3
0.3
0.3
0.8
0.8
VCC + 0.2
Notes amended
*1 If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins
open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by
connecting them to VCC, for instance. Set Vref AV CC.
*3 The values are for VRAM LPV CC < 3.0 V, VIH min = VCC × 0.9, and VIL max =
0.3 V.
(Incorrect)20MHz
(Correct)Condition
Data Bus Width of H'EBC0 to H'EFBF
(Incorrect)16/32
(Correct)8/16/32*

12 Page





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