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AP0202AT Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer AP0202AT
Beschreibung High-Dynamic Range (HDR) Image Signal Processor
Hersteller ON Semiconductor
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Gesamt 30 Seiten
AP0202AT Datasheet, Funktion
Advance
AP0202AT: Image Signal Processor (ISP)
Features
AP0202AT High-Dynamic Range (HDR) Image
Signal Processor (ISP)
AP0202AT Datasheet, Rev. 4
For the latest product datasheet, please visit www.onsemi.com
Features
• Up to 2.0 Mp (1920x1080) ON Semiconductor sensor
support
• 30 fps at 1080p, 45 fps at 1.2Mp, 60 fps at 720p
(Optimized for operation with HDR sensors)
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz auto
flicker detection and avoidance
• Adaptive Local Tone Mapping (ALTM)
• Two-wire serial programming interface (CCIS)
• Parallel output
• Configurable through low-cost SPI Flash and
EEPROM devices
• High-level host command interface
• Standalone operation supported
• Up to 7 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
Applications
• Surround, rear and front view cameras
• Blind spot / side mirror replacement cameras
• Automotive viewing/processing fusion cameras
Table 1:
Key Performance Parameters
Parameter
Image sensor
interfaces
Input Data
FOrmat
Value
Parallel and HiSPi
Parallel: 12 bit SDR (linear) or
12 bit HDR companded.
Output interface
Output format
Maximum
resolution
Input clock range
Output pixel clock
maximum
Supply voltage
Operating temp.
(Ambient)
Power
consumption
HiSPI: 12 bit SDR (linear) or
12/14 bit HDR companded
Up to 24-bit parallel1
RGB888, RGB565, YUV422 8-/10-bit1
1920 x 1080 (2.0 Mp)
10 - 29 MHz
125 MHz2
VDDIO_S
VDDIO_H
VDD_REG
VDD
VDD_PLL
VDD_PHY
VDDIO_OTPM
–40°C to +105°C
1.8 or 2.8 V nominal
1.8 or 2.8 or 3.3 V
nominal
1.8 V nominal
1.2 V nominal
1.2 V nominal
2.8 V nominal
2.5 to 3.3 V nominal
250 mW
Notes: 1. Maximum frame rates depend on output interface and
data format configuration used.
2. Maximum pixel clock rates depend on IO voltage.
AP0202AT/D Rev. 4, 9/15 EN
1 ©Semiconductor Components Industries, LLC 2015,
‡This document contains information on a new product. Specifications and information herein are subject to change without notice.






AP0202AT Datasheet, Funktion
Advance
AP0202AT: Image Signal Processor (ISP)
General Description
General Description
ON Semiconductor's AP0202AT Image Signal Processor (ISP) is optimized for use with
HDR (High Dynamic Range) sensors. The AP0202AT provides full auto-functions
support (AWB and AE) and ALTM (Adaptive Local Tone Mapping) to enhance HDR
images and advanced noise reduction which enables excellent low-light performance.
Functional Overview
Figure 1 shows the typical configuration of the AP0202AT in a camera system. On the
host side, a two-wire serial or SPI interface is used to configure the operation of the
AP0202AT, and image data is transferred using the parallel interface between the
AP0202AT and the host. The AP0202AT interface to the sensor supports a parallel inter-
face or HiSPi interface.
Figure 1: AP0202AT Connectivity
AP0202AT/D Rev. 4, Pub. 9/15 EN
6 ©Semiconductor Components Industries, LLC, 2015.

6 Page









AP0202AT pdf, datenblatt
Advance
AP0202AT: Image Signal Processor (ISP)
System Interfaces
Table 3:
Pin Descriptions
Name
GPIO_[6:1]
TEST
RESERVED_[1:0]
VDDIO_S
VDDIO_H
VDD_PLL
VDD
VDDIO_OTPM
VDD_PHY
GND
VDD_REG
LDO_OP
FB_SENSE
Type
I/O
Input
Input
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Output
Input
Description
General purpose digital I/O.
Must be tied to GND in normal operation.
Must be tied to GND in normal operation.
Sensor I/O power supply.
Host I/O power supply.
PLL supply.
Core supply.
OTPM power supply.
PHY IO voltage for HiSPi
Ground
Input to on-chip 1.8V to 1.2V regulator.
Output from on chip 1.8V to 1.2V regulator.
On-chip regulator sense signal.
Table 4:
Package Pinout
1
2 34
5
A RESERVED_0
VDDIO_H
M_SDATA
DIN0
VDD
B SCLK
GPIO_6 EXTCLK_OUT M_SCLK
DIN1
SPI_SCLK
RESERVED_
SDATA
C1
GPIO_5
TRIGGER_OUT/
GPIO_0
D SPI_SDO
SPI_SDI SPI_CS_BAR SADDR RESET_BAR_OUT
E VDD
GPIO_1
STANDBY
GND
GND
F VDDIO_OTPM
GPIO_2
GPIO_3 RESET_BAR
GND
G TEST
GPIO_4 FRAME_SYNC LV_OUT
DOUT16
H META_LINE_VALID FV_OUT
DOUT21
DOUT18
DOUT14
J PIXCLK_OUT
DOUT22
DOUT19
DOUT17
DOUT13
K DOUT23
VDDIO_H
DOUT20
DOUT15
VDD
6
DIN5
DIN4
DIN3
DIN2
GND
GND
DOUT12
DOUT8
DOUT10
DOUT11
7
DIN10
DIN9
DIN8
DIN7
DIN6
GND
DOUT5
DOUT6
DOUT7
DOUT9
8
LV_IN
DIN11
PIXCLK_IN
9
VDDIO_S
HiSPi1N
HiSPiCN
VDD_PHY
GND
EXTCLK
EXT_REG
DOUT2
DOUT3
DOUT4
HiSPi0N
DGND
XTAL
ENLDO
FB_SENSE
DOUT0
DOUT1
10
FV_IN
HiSPi1P
HiSPiCP
HiSPi0P
VDDIO_H
VDD
VDD_PLL
VDD_REG
LDO_OP
GND
AP0202AT/D Rev. 4, Pub. 9/15 EN
12
©Semiconductor Components Industries, LLC, 2015.

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