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LE25CB643TT-BH Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer LE25CB643TT-BH
Beschreibung 64 kb SPI CMOS Serial EEPROM
Hersteller ON Semiconductor
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Gesamt 17 Seiten
LE25CB643TT-BH Datasheet, Funktion
Ordering number : ENA2255
LE25CB643TT-BH
CMOS IC
64 kb SPI CMOS Serial EEPROM
http://onsemi.com
Overview
The LE25CB643TT-BH (hereinafter referred to as ‘this device’) is serial peripheral interface EEPROM (Electrically
Erasable and Programmable ROM). This device realizes high speed and a high level reliability by incorporating high
performance CMOS EEPROM technology. This device is compatible with SPI memory protocol, therefore it is best
suited for application that requires re-writable nonvolatile parameter memory. And this device has 32bytes page write
function for high speed data re-write.
Function
Capacity
: 64k bits (8k × 8 bits)
Single supply voltage
: 2.7V to 5.5V
Operating temperature
: -40ºC to +85ºC
Interface
: SPI Mode0 and Mode3
correspondence
Operating clock frequency : 5MHz
Low Power consumption
: Standby
: Read
: 3µA (max.)
: 1mA (max.)
Micro8
: Write
: 3mA (max.)
Automatic page write mode : 32 Bytes
Write cycle time
Erase/Write cycles
: 5ms
: 106 cycles
Data Retention
: 20 years
High reliability
: Adopts proprietary symmetric memory array configuration (USP6947325)
Incorporates a feature to prohibit write operations under low voltage conditions.
Package
: LE25CB643TT-BH Micro8
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of this data sheet.
Semiconductor Components Industries, LLC, 2013
December, 2013
D1813HKPC 20131129-S00001 No.A2255-1/17






LE25CB643TT-BH Datasheet, Funktion
LE25CB643TT-BH
Table 1: Commands Summary
Command
Write enable
(WREN)
Write disable
(WRDI)
Status Register Read
(RDSR)
Status Register Write
(WRSR)
The 1st bus
cycle
06h
04h
05h
01h
Read
03h
Write
02h
The 2nd bus
cycle
DATA
A15-A8
A15-A8
The 3rd bus
cycle
A7-A0
A7-A0
The 4th bus
cycle
PD *1
The 5th bus
cycle
PD *1
The 6th bus
cycle
PD *1
Definition of Table 1 :
h = hexadecimal notation, A15 to A13 are don't care for all commands.
*1. PD: page write data. The arbitrary numbers of data of 1 to 32 bytes of byte unit for input.
The n-th bus
cycle
PD *1
No.A2255-6/17

6 Page









LE25CB643TT-BH pdf, datenblatt
LE25CB643TT-BH
BP0, BP1 (Bit2, 3)
Block protection BP0 and BP1 can set up the memory address area to be protected. Refer to Table 3 for setting
conditions.
Table 3: Protection level setting conditions
Protection level
Status Register bit
(Level)
BP1 BP0
all area unprotect ion
(0)
0
0
Upper 1/4 protection
(1)
0
1
Upper 1/2 protection
(2)
1
0
all area protection
(3)
1
1
Protection area
nothing
1800h to 1FFFh
1000h to 1FFFh
0000h to 1FFFh
SRWP (Bit7)
Status Register Write protection SRWP protects Status Register. When "1" state and WP pin are logic low levels, as for
a Status Register Write command, they are disregarded, and as for BP0, BP1 and of a Status Register, and SRWP is
protected. When WP pin is a logic high level, a Status Register is not protected irrespective of the state of SRWP.
SRWP setting conditions are shown in Table 4.
Table 4: SRWP setting conditions
WP pin
SRWP
Mode
10
Software Protect
00
(SPM)
11
Hardware Protect
01
(HPM)
Status Register protection state
Unprotect
Protect
Protected Area
Protect
Protect
Unprotected Area
Unprotect
Unprotect
Bit4, Bit5, Bit6 are reserve bit.
3. Write Enable
Write Enable sets a Status Register WEN to "1" state. In order to perform the following operation, it is necessary to
execute a Write Enable command first. A timing waveform is shown in Figure7. Write Enable command consists of
only the 1st bus cycle, OP-code is 06h.
Write
Status Register Write
No.A2255-12/17

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