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PDF NB3U1548C Data sheet ( Hoja de datos )
| Número de pieza | NB3U1548C | |
| Descripción | 3.3V/2.5V/1.8V/1.5V 160MHz 1:4 LVCMOS/LVTTL Low Skew Over Voltage Tolerant Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB3U1548C
3.3V/2.5V/1.8V/1.5V 160 MHz
1:4 LVCMOS/LVTTL Low
Skew Over Voltage Tolerant
Fanout Buffer
Description
The NB3U1548C is an LVCMOS, overvoltage tolerant clock fanout
buffer targeted for clock generation in high performance
telecommunication, networking and computing applications. The
device is optimized for low skew clock distribution in low voltage
applications. The input overvoltage tolerance enables using this
device in mixed mode voltage applications. An output enable pin
controls whether the outputs are in the active or high impedance state.
Guaranteed output skew characteristics make the NB3U1548C ideal
for those applications demanding well defined performance and
repeatability. The NB3U1548C is packaged in a small SOIC−8 and in
an TSSOP−8 package.
Features
• Low skew 1:4 Fanout Buffer
• Supports 3.3 V, 2.5 V, 1.8 V and 1.5 V Power Supplies
• LVCMOS Input and Output Levels
• 3.6 V Overvoltage Tolerance at the Clock and Control Inputs
• Supports Clock Frequencies up to 160 MHz
• LVCMOS Compatible Control Input for Output Disable
• Output Disabled to a High Impedance State
• −40°C to 85°C Ambient Operating Temperature
• Available in Pb−Free RoHS Compliant Packages (SOIC−8,
TSSOP−8)
• These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948S
MARKING
DIAGRAMS
8
1548C
ALYWG
G
1
8
154
YWW
AG
1
A = Assembly Location
L = Wafer Lot
Y = Year
W, WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 3
1
Publication Order Number:
NB3U1548C/D
1 page  
NB3U1548C
Table 6. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min Typ Max Units
AC CHARACTERISTICS, VDD = 3.3 V + 5%, TA = −405C to 855C
fOUT
tpLH
Output Frequency
Propagation Delay
(low to high transition); (Notes 4, 8)
160 MHz
0.7 2.1 ns
tpHL Propagation Delay
(high to low transition); (Notes 4, 8)
0.7 2.1 ns
tPLZ, tPHZ
tPZL, tPZH
tsk(o)
Disable Time, (active to high−impedance)
Enable Time, (high−impedance to active)
Output Skew; (Notes 5, 6)
10 ns
10 ns
250 ps
tsk(pp)
Part−to−Part Skew; (Notes 5, 7)
800 ps
tjit
Buffer Additive Phase Jitter, RMS
25 MHz, Integration Range:
12 kHz − 5 MHz
0.094
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
0.33
48
1.2 ns
53 %
AC CHARACTERISTICS, VDD = 2.5 V + 5%, TA = −405C to 855C
fOUT
Output Frequency
tpLH Propagation Delay
(low to high transition); (Notes 4, 8)
160 MHz
0.8 2.0 ns
tpHL Propagation Delay
(high to low transition); (Notes 4, 8)
0.8 2.0 ns
tPLZ, tPHZ
tPZL, tPZH
tsk(o)
Disable Time (active to high−impedance)
Enable Time (high−impedance to active)
Output Skew; (Notes 5, 6)
10 ns
10 ns
250 ps
tsk(pp)
Part−to−Part Skew; (Notes 5, 7)
800 ps
tjit
Buffer Additive Phase Jitter, RMS
25 MHz, Integration Range:
12 kHz − 5 MHz
0.076
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
0.33
45
1.2 ns
53 %
AC CHARACTERISTICS, VDD = 1.8 V + 0.15 V, TA = −405C to 855C
fOUT
Output Frequency
tpLH Propagation Delay
(low to high transition); (Notes 4, 8)
160 MHz
1.1 2.8 ns
tpHL Propagation Delay
(high to low transition); (Notes 4, 8)
1.1 2.8 ns
tPLZ, tPHZ
tPZL, tPZH
tsk(o)
Disable Time (active to high−impedance)
Enable Time (high−impedance to active)
Output Skew; (Notes 5, 6)
10 ns
10 ns
250 ps
tsk(pp)
Part−to−Part Skew; (Notes 5, 7)
800 ps
tjit
Buffer Additive Phase Jitter, RMS
25 MHz, Integration Range:
12 kHz − 5MHz
0.193
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Characterized up to FOUT ≤ 150 MHz.
4. Measured from the VDD/2 of the input to VDD/2 of the output.
5. This parameter is defined in accordance with JEDEC Standard 65.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
8. With rail to rail input clock.
www.onsemi.com
5
5 Page 
NB3U1548C
PACKAGE DIMENSIONS
0.20 (0.008) T U S
2X L/2
L
PIN 1
IDENT
0.20 (0.008) T U S
TSSOP−8
CASE 948S
ISSUE C
8x K REF
0.10 (0.004) M T U S V S
85
B
−U−
14
J J1 ÉÉÉÇÇÉÉÉÇÇÉÉÉÇÇÉÉÉÇÇ
K1
K
A SECTION N−N
−V−
0.076 (0.003)
−T− SEATING
PLANE
D
C
G
DETAIL E
−W−
N 0.25 (0.010)
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 2.90 3.10 0.114 0.122
B 4.30 4.50 0.169 0.177
C --- 1.10 --- 0.043
D 0.05 0.15 0.002 0.006
F 0.50 0.70 0.020 0.028
G 0.65 BSC
0.026 BSC
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
F
DETAIL E
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
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11
NB3U1548C/D
11 Page | ||
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| PDF Descargar | [ Datasheet NB3U1548C.PDF ] | |
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