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NL3HS644 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NL3HS644
Beschreibung 2:1 MIPI D-PHY (1.5 Gbps) 4-Data Lane Switch
Hersteller ON Semiconductor
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Gesamt 8 Seiten
NL3HS644 Datasheet, Funktion
NL3HS644
2:1 MIPI D-PHY (1.5 Gbps)
4-Data Lane Switch
The NL3HS644 is a 4−data lane MIPI, D−PHY switch. This
single−pole double−throw (SPDT) switch is optimized for switching
between 2 high−speed or low−power MIPI sources. The NL3HS644 is
designed for MIPI specifications and allows connection to a CSI or
DSI module.
Features
Operating Supply: VCC = 1.65 V to 4.5 V
Switch Signal Range: 0 to VCC
Signal Types: MIPI, D−PHY
ON−Resistance:
RON = 8 W (Typ) HS MIPI
RON = 7.9 W (Typ) LP MIPI
ON−Resistance Mismatch:
DRON = 0.09 W (Typ) HS MIPI
DRON = 0.17 W (Typ) LP MIPI
ON Resistance Flatness:
RON_FLAT = 0.03 W (Typ) HS MIPI
RON_FLAT = 0.46 W (Typ) LP MIPI
Supply Current: ICC = 55 mA (Max)
Hi−Z Supply Current: ICCZ = 5 mA (Max)
Off−Isolation: OIRR = −27 dB (Typ)
Crosstalk: XTALK = −28 dB (Typ)
Bandwidth: BW = 1,050 MHz (Typ)
Channel to Channel Skew: tSK = 63 ps (Typ)
ON Capacitance: CON = 12.6 pF
36−Ball WLCSP Package, 2.36 mm x 2.36 mm
This device is Pb−Free, Halogen−Free/BFR−Free and are
RoHS−Compliant
www.onsemi.com
WLCSP36
FC SUFFIX
CASE 567LR
MARKING DIAGRAM
XXXXXX
AWLYWW
G
XXXXXX = Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 8 of this data sheet.
Figure 1. Typical Application – Mobile Phone
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 2
1
Publication Order Number:
NL3HS644/D






NL3HS644 Datasheet, Funktion
NL3HS644
Timing Diagrams
Operating Level
VCC
tINIT
Transactions Not Valid
Transactions Valid
Figure 4. tINIT, Initialization Time
SEL /
OE
tF =
2.5 ns
90 %
50 %
10 %
OUTPUT
OUTPUT
tON /
tEN
tR =
2.5 ns
90 %
50 %
10 %
tOFF /
tDIS
VCC
GND
10 % x V OH
VOL
90 % x V OH VOH
Figure 5. tEN, tDIS, tON, tOFF Times
SEL
VCC
VOH
VA and V B
INPUT
GND
OUTPUT
90 % x V O
90 % x V O
GND
VO
tVOL
BBM
Figure 6. tBBM, Break−Before−Make Time
P−Ch/
0.2 VPP N−Ch
Midpoint
N−Ch/
P−Ch
P−Ch/
N−Ch
N−Ch/
P−Ch
Midpoint
tSK(O)
tSK(O)
Figure 7. tSK(O), Channel−to−Channel
Single−Ended
P−Ch/N−Ch
Same Channel
0.2 VPP
Midpoint
tSK(P)
Figure 8. tSK(P), Same Channel Opposite
Transitions
www.onsemi.com
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