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NCP51401 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NCP51401
Beschreibung Termination Regulator
Hersteller ON Semiconductor
Logo ON Semiconductor Logo 




Gesamt 7 Seiten
NCP51401 Datasheet, Funktion
NCP51401
3 Amp VTT Termination
Regulator DDR1, DDR2,
DDR3, LPDDR3, DDR4
The NCP51401 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration.
The NCP51401 maintains a fast transient response and only requires
a minimum output capacitance of 20 mF. The NCP51401 supports a
remote sensing function and all power requirements for DDR VTT bus
termination. The NCP51401 can also be used in low−power chipsets
and graphics processor cores that require dynamically adjustable
output voltages.
The NCP51401 is available in the thermally−efficient DFN10
Exposed Pad package, and is rated both Green and Pb−free.
Features
Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
PVCC Voltage Range: 1.1 to 3.5 V
Integrated Power MOSFETs
Source and Sink Termination Regulator with Droop Compensation
Fast Load−Transient Response
PGOOD − Logic output pin to Monitor VTT Regulation
EN − Logic input pin for Shutdown mode
VRI − Reference Input Allows for Flexible Input Tracking Either
Directly or Through Resistor Divider
Remote Sensing (VTTS)
Built−in Under Voltage Lockout and Over Current Limit
Thermal Shutdown
Small, Low−Profile 10−pin, 3x3 DFN Package
These Devices are Pb−Free and are RoHS Compliant
Applications
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Chipset/RAM Supplies as Low as 0.5 V
Active Bus Termination
www.onsemi.com
DFN10, 3x3, 0.5P
CASE 506CL
MARKING DIAGRAM
51401
ALYWG
G
51401
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTION
VRI
PVCC
VTT
PGND
VTTS
+
1
2
3
4
5
GND
10 VCC
9 PGOOD
8 GND
7 EN
6 VRO
Exposed Pad
ORDERING INFORMATION
Device
Package Shipping
NCP51401MNTXG DFN10 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 0
1
Publication Order Number:
NCP51401/D






NCP51401 Datasheet, Funktion
NCP51401
VTT Startup Time
In order to speed up the time it takes a modern computer
to Boot−up or Resume after Stand−by, some newer
motherboard specs require VTT to rise from 0 V to 95% of
VTT in less than 35 msec. This new requirement is met in the
new ON Semiconductor NCP51401, NCP51402 and
NCP51403 devices.
VTT Droop Compensation
Droop compensation is a technique to reduce error voltage
due to a transient, or as a design tradeoff, to reduce system
cost for a given transient magnitude, by using smaller, less
expensive capacitors. Figure 2 shows the transient response
in a system without droop compensation and is showing a
peak−to−peak error voltage of ±30 mV. Figure 3 shows the
same magnitude of transient response, but this time the
regulation is performed *with* droop compensation. For
example the magnitude of the transient in Figure 3 is
+30 mV = +20 mV – (−10 mV) which is the same magnitude
as in Figure 2, but since the output voltage is allowed to sag
10 mV when loaded (as opposed to the “perfect” Load
Regulation, i.e. 0 mV of VTT output voltage sag as shown
in Figure 2) then this same +30 mV transient starts at
−10 mV and now only peaks to +20 mV. The net result is that
with 10 mV of droop, the overall, peak−to−peak error
voltage has been reduced from ±30 mV to ±20 mV.
Figure 2.
Legacy DDR2/3, DDR4 and Droop Compensation
When the popular, now industry−standard, 51200−
compatible devices were first introduced, the PC memory
industry was transitioning from DDR2 (VTT = 900 mV) to
DDR3 (VTT = 750 mV) and a value of ±14 mV of droop
compensation per ±1.5 amps of DC current was
designed−in. This value of droop was appropriate for the
DDR2 and DDR3 memory in use at the time, but this amount
of droop has now become excessive for DDR4. For example
for DDR4 with a VTT voltage of 600 mV, the 5% error
tolerance is ±30 mV, which leaves no transient−response
margin for a DC load of ±2 amps. This excessive DDR2/3
droop compensation issue of using 51200 devices in newer
DDR4 applications has been solved in the new
ON Semiconductor NCP51402 and NCP51403 devices,
which have no droop compensation for improved,
high−current DDR4 transient response.
Figure 3.
VTT Capacitor Selection
Many 51200−compatible devices have specified VTT
capacitor ESR requirements and must be loaded with at least
20 mF of ceramic capacitance in order to guarantee stability.
In contrast, the NCP51400, NCP51401 and NCP51402 were
all designed to be stable with a wide range of ESR and can
use both ceramic and higher−ESR, polymer capacitors.
Extending the NCP5140x family of parts, in applications
that have specified phase margin requirements, we have
introduced the NCP51403 which has 45° of phase margin
when VTT is loaded with a ceramic capacitance of 40 mF.
However just like our competitor’s 51200−compatible
devices, the NCP51403 cannot be loaded solely with
polymer capacitors because the 45° phase margin reduces
the ESR−stability range of the VTT capacitor.
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