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PDF MTP2N40E Data sheet ( Hoja de datos )
| Número de pieza | MTP2N40E | |
| Descripción | Power Field Effect Transistor | |
| Fabricantes | ON Semiconductor | |
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MTP2N40E
Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect
Transistor
N−Channel Enhancement−Mode Silicon
Gate
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
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TMOS POWER FET
2.0 AMPERES, 400 VOLTS
RDS(on) = 3.5 W
TO−220AB
CASE 221A−06
Style 5
D
®G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−Source Voltage
Drain−Gate Voltage (RGS = 1.0 MΩ)
Gate−Source Voltage — Continuous
Gate−Source Voltage — Non−Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 μs)
Total Power Dissipation
Derate above 25°C
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
400
400
± 20
± 40
2.0
1.5
6.0
40
0.32
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Operating and Storage Temperature Range
TJ, Tstg
−55 to 150
°C
Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 Ω)
EAS 45 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
3.13 °C/W
62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Publication Order Number:
MTP2N40E/D
1 page  
MTP2N40E
12 400
10 QT
300
8 VGS
6
Q1
Q2
200
ID = 2 A
4 TJ = 25°C
100
2
0 Q3
02
4
VDS
68
0
QT, TOTAL CHARGE (nC)
Figure 7. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
VDD = 200 V
ID = 2 A
VGS = 10 V
TJ = 25°C
td(off)
10 tf
tr
td(on)
1
1 10
RG, GATE RESISTANCE (OHMS)
Figure 8. Resistive Switching Time
Variation versus Gate Resistance
1
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
2
VGS = 0 V
TJ = 25°C
1.5
1
0.5
0
0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
shown in the accompanying graph (Figure 11). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For
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