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PDF MTV16N50E Data sheet ( Hoja de datos )
| Número de pieza | MTV16N50E | |
| Descripción | Power Field Effect Transistor | |
| Fabricantes | ON Semiconductor | |
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MTV16N50E
Advance Information
TMOS E−FET.™
Power Field Effect
Transistor
D3PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
This high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high speed switching
applications in power supplies, converters, PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
http://onsemi.com
TMOS POWER FET
16 AMPERES, 500 VOLTS
RDS(on) = 0.40 W
D3PAK Surface Mount
CASE 433−01
Style 2
D
N−Channel
®G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
Gate−to−Source Voltage — Continuous
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 μs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 16 Apk, L = 6.7 mH, RG = 25 Ω )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
RθJC
RθJA
RθJA
TL
Value
500
500
±20
16
9.0
60
180
1.4
2.0
−55 to 150
860
0.7
62.5
35
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
Publication Order Number:
MTV16N50E/D
1 page  
MTV16N50E
15 500
12 QT
400
VGS
9
Q1
Q2
300
6 200
TJ = 25°C
3 ID = 16 A 100
Q3 VDS
00
0 10 20 30 40 50 60 70 80 90 100
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10000
1000
TJ = 25°C
ID = 16 A
VDD = 250 V
VGS = 10 V
td(off)
td(on)
100
10
1
tr
tf
10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
10
14
TJ = 25°C
12 VGS = 0 V
10
8
6
4
2
0
0 0.2 0.4 0.6 0.8 1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For
http://onsemi.com
5
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| PDF Descargar | [ Datasheet MTV16N50E.PDF ] | |
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