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PL663-18 Schematic ( PDF Datasheet ) - Micrel

Teilenummer PL663-18
Beschreibung Analog Frequency Multiplier
Hersteller Micrel
Logo Micrel Logo 




Gesamt 14 Seiten
PL663-18 Datasheet, Funktion
Analog Frequency Multiplier
PL663-xx XO Families
DESCRIPTION
Analog Frequency Multipliers TM (AFMs) are the
industry’s first “Balanced Oscillatorutilizing analog
multiplication of the fundamental frequency (at
double or quadruple frequency), combined with an
attenuation of the fundamental of the reference
crystal, without using a phase-locked loop (PLL), in
CMOS technology.
Patent pending PL663-xx family of AFM products
can achieve up to 800 MHz differential LVPECL,
LVDS, or single-ended LVCMOS output with little
jitter or phase noise deterioration.
PL663-xx family of products utilizes a low-power
CMOS technology and is housed in GREEN/ RoHS
compliant 16-pin TSSOP and 3x3 QFN packages.
FEATURES
Non-PLL frequency multiplication
Input frequency from 30-200 MHz
Output frequency from 60-800 MHz
Low phase noise and jitter (equivalent to fundamental
at the output frequency)
Ultra-low jitter
o RMS phase jitter < 0.25 ps (12 kHz to 20 MHz)
o RMS period jitter < 2.5 ps typ.
Low phase noise
o -145 dBc/Hz @ 100 kHz offset from 155.52 MHz
o -150 dBc/Hz @ 10 MHz offset from 155.52 MHz
Low input frequency eliminates the need for expensive
crystals
Differential LVPECL/LVDS, or single-ended LVCMOS
output
Single 2.5V or 3.3V +/- 10% power supply
Optional industrial temperature range (-40C to
+85C)
Available in 16-pin GREEN/RoHS compliant TSSOP,
and 16-pin 3x3 QFN packages.
Figure 1: 2X AFM Phase Noise at 212.5 MHz (106.25 MHz 3rd overtone crystal)
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev. 02/18/10 Page 1






PL663-18 Datasheet, Funktion
Analog Frequency Multiplier
PL663-xx XO Families
There are two default variables that normally will not need to be modified. These are Cpad, and C11 and
are found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively.
LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a
leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of
these and they are assumed to be approximately symmetrical so you only need to enter this inductance
once in cell B23.
Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a
leaded part is used.
Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM
Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency.
Internal Capacitor Selection by Device
Device Number
Cinternal (pF)
PL663-0X
PL663-1X
PL663-2X
2X
46.500
14.625
14.625
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev. 02/18/10 Page 6

6 Page









PL663-18 pdf, datenblatt
Analog Frequency Multiplier
PL663-xx XO Families
PACKAGE PIN DESCRIPTION AND ASSIGNMENT
DNC
GNDOSC
DNC
XIN
XOUT
OE
DNC
GNDANA
1
2
3
4
5
6
7
8
16 L2X
15 VDDOSC
14 VDDANA
13 OESEL
12 VDDBUF
11 QBAR
10 Q
9 GNDBUF
OESEL
VDDANA
VDDOSC
L2X
12 11 10 9
13 8
14 7
PL663-XX
15 6
16 5
1234
GNDANA
DNC
OE
XOUT
2x AFM Package Pin Out
PIN ASSIGNMENTS
Name
Pin # Type
Description
DNC
GNDOSC
XIN
XOUT
OE
GNDANA
GNDBUF
Q
QBAR
VDDBUF
OESEL
VDDANA
VDDOSC
1,3,7
2
4
5
6
8
9
10
11
12
13
14
15
L2X 16
I Do Not Connect.
P GND connection for oscillator.
I Input from crystal oscillator circuitry.
O Output from crystal oscillator circuitry.
I Output Enable input. See “OE LOGIC SELECTION TABLE”.
P GND connection.
P GND connection.
O PECL/LVDS/CMOS output.
O Complementary PECL/LVDS output or in-phase CMOS.
P
VDD connection for output buffer circuitry. VDDBUF should be separately decoupled
from other VDDs whenever possible.
I
Selector input to choose the OE control logic (see “OE SELECTION TABLE”). If no
connection is applied, value will be set to default through internal pull-down resistor.
P
VDD connection for analog circuitry.VDDANA should be separately decoupled from
other VDDs whenever possible.
P
VDD connection for oscillator. VDD should be separately decoupled from other VDDs
whenever possible.
External inductor connection. The inductor is recommended to be a high Q small size
I
0402 or 0603 SMD component, and must be placed between L2X and adjacent
VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects
and to maintain inductor Q.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev. 02/18/10 Page 12

12 Page





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