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PL602-39 Schematic ( PDF Datasheet ) - Micrel

Teilenummer PL602-39
Beschreibung 750kHz - 800MHz Low Phase Noise Multiplier XO
Hersteller Micrel
Logo Micrel Logo 




Gesamt 10 Seiten
PL602-39 Datasheet, Funktion
PL602-35/-37/-38/-39
750kHz 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FE AT UR E S
PIN CONFIGURATION
Selectable 750kHz to 800MHz range.
Low phase noise output
-127dBc/Hz for 155.52MHz @ 10kHz offset
-115dBc/Hz for 622.08MHz @ 10kHz offset
LVCMOS (PL602-37), LVPECL (PL602-35 and
PL602-38) or LVDS (PL602-39) output.
12MHz to 25MHz crystal input.
No external crystal load capacitors required.
Output Enable selector.
Selectable /16 to x32 frequency divider/multiplier.
3.3V operation.
Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages.
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
GND
GND
1
1
6
2
1
5
3
1
4
4
1
3
5
1
2
6
1
1
7
1
0
89
TSSOP-16L
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
DESCRIPTION
The PL602-35 (LVPECL with inverted OE), PL602-37
(LVCMOS), PL602-38 (LVPECL), and PL602-39
(LVDS) are high performance and low phase noise XO
IC chips. They provide phase noise performance as
low as 127dBc at 10kHz offset (at 155MHz), by multi-
plying the input crystal frequency up to 32x. The very
low jitter makes them ideal for a wide range of applica-
tions, including SONET/SDH and FEC. They accept
fundamental parallel resonant mode crystals from
12MHz to 25MHz.
XOUT
SEL3^
SEL2^
OE
12
13
11 10
9
8
14
PL602-3x
7
15 6
16 5
123 4
GND
CLKC
VDD
CLKT
BLOCK DIAGRAM
SEL[3:0]
XIN
XOUT
Oscillator
Amplifier
w/
integrated
load cap.
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
CLKC
QFN-16L
^: Internal pull-up
*: On QFN package, PL602-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL602-37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for details.
Note: On QFN package there is a large center pad for thermal relief.
This pad needs to be connected to GND.
CLKT OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PL602-3x
PL602-38
PL602-35
PL602-37
PL602-39
0 (Default)
1
0
1 (Default)
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by LVPECL levels for PL602-38
Logical states defined by LVCMOS levels for PL602-37/-39
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 1






PL602-39 Datasheet, Funktion
PL602-35/-37/-38/-39
750kHz 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
VOD
VOD
VOH
VOL
VOS
VOS
IOXD
IOSD
247 355 454 mV
-50 50 mV
RL = 100Ω
(see figure)
1.4 1.6 V
0.9 1.1
V
1.125
1.2 1.375
V
0 3 25 mV
Vout = VDD or GND
VDD = 0V
1 10 uA
-5.7 -8 mA
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
Differential Clock Rise Time
Differential Clock Fall Time
tr
tf
CONDITIONS
RL = 100Ω
CL = 10 pF
(see figure)
MIN. TYP. MAX. UNITS
0.2 0.7 1.0 ns
0.2 0.7 1.0 ns
LVDS Levels Test Circuit
OUT
OUT
VO D
50
VO S
50
LVDS Switching Test Circuit
OUT
CL = 10pF
VDIF F
OUT
CL = 10pF
RL = 100
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
VDIF F
0V
20%
80%
tR
80%
20%
tF
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 6

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