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PDF PL685-28 Data sheet ( Hoja de datos )
| Número de pieza | PL685-28 | |
| Descripción | 19MHz to 250MHz Low Phase-Noise XO | |
| Fabricantes | Micrel | |
| Logotipo |  |
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(Preliminary) PL685-28
FE AT UR E S
19MHz to 250MHz Low Phase-Noise XO
PAD CONFIGURATION
< 0.6ps RMS phase jitter (12kHz to 20MHz) at
155.52MHz
30ps max peak to peak period jitter
8bit Switch Capacitor for ±50PPM crystal CLoad
tuning
о Load Capacitance Tuning Range: 8pF to 12pF
Ultra Low-Power Consumption
о < 90 mA @155MHz PECL output
о <10A at Power Down (PDB) Mode
Input Frequency:
о Fundamental Crystal: 19MHz to 40MHz
Output Frequency:
о 19MHz to 250MHz output.
Output types: LVPECL.
Programmable OE input polarity selection.
Power Supply: 3.3V, ±10%
Operating Temperature Ranges:
о Commercial: 0C to 70C
о Industrial: -40C to 85C
Available in Die or Wafer
DESCRIPTION
The PL685-28 is a Dual LC core monolithic IC clock,
capable of maintaining sub-1ps RMS phase jitter,
while covering a wide frequency output range up to
250MHz, without the use of external components.
The high performance and high frequency output is
achieved using a low cost fundamental crystal of
between 19MHz and 40 MHz. The PL685-28 is
designed to address the demanding requirements of
high performance applications such as Fiber
Channel, serial ATA, Ethernet, SAN, SONET/SDH,
etc.
65 mil
SCLK 9
8
Die ID
OE/PDB/
SDIO
DNC
10
11
GND_ANA
GND_DIG
GND_BUF
12
13
14
(0,0)
PL685
(1650,2250)
7
6 VDD_ANA
5 VDD_DIG
4 VDD_BUF
3 QB
2 VDD_BUF
1Q
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
65 x 88.6 mil
GND
80 micron x 80 micron
8 mils
OUTPUT ENABLE CONTROL
OE Select
(Programmable)
OE
State
0
0 (Default)
1
Output enabled
Tri-state
1 (Default)
0
1 (Default)
Tri-state
Output enabled
BLOCK DIAGRAM
OE/PDB
XIN/REF
XOUT
Xtal
Osc
(Default pre-programmed output path)
PD/CP
LF – HF
LCVCOs
Pre-scalar
4/6
/2
Programmable Function
M Divider
(5 bit)
P Divider
(4 bit)
/2
Q
QB
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/02/11 Page 1
1 page  
(Preliminary) PL685-28
19MHz to 250MHz Low Phase-Noise XO
4. CRYSTAL SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
Crystal Resonator Frequency
Crystal Cload
Shunt Capacitance
Recommended ESR
FXIN
CL_ Crysta l
C0_ Crysta l
RE
Parallel Fundamental Mode
VDD = 3.3V, programmable
AT cut
MIN TYP MAX UNITS
19 40 MHz
8 12 pF
3.5 pF
50 Ω
5. JITTER SPECIFICATIONS
PARAMETERS
FREQUENCY
CONDITIONS
MIN TYP MAX UNITS
RMS Phase Jitter
155.52MHz 10kHz to 20MHz, XIN=38.88MHz
0.56
ps
Period Jitter, Pk-to-Pk 155.52MHz 10K cycles, XIN=38.88MHz
30 ps
6. PHASE NOISE SPECIFICATIONS
PARAMETERS
Freq.
(MHz)
@
10Hz
Phase Noise, relative
to carrier (typical)
155.52
-58
@
100Hz
-95
@
1KHz
-119
@@
10KHz 100KHz
-124 -129
@
1MHz
135
@
10MHz
148
UNITS
dBc/Hz
7. LVPECL OUTPUTS (Q, QB)
PARAMETERS
SYMBOL
Output High Voltage
VOH
Output Low Voltage
VOL
Output Frequency
Output Rise, Fall Times
Output Voltage Swing
Fout
tr, tf
Vpp
CONDITIONS
Q, QB
Standard LVPECL Termination,
VDD = 3.3V
3.3V
20% - 80% of Qpp/QBpp
Q, QB
MIN
2.275
1.490
19
550
TYP
2.350
1.600
200
800
MAX
2.420
1.680
250
300
900
UNITS
V
V
MHz
ps
mV
LVPECL Levels Test Circuit
LVPECL Transistion Time Waveform
DUTY CYCLE
OUT
VDD
45 - 55%
55 - 45%
50?
2.0V
OUT
80%
50%
50? 20%
OUT
OUT tR tF
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/02/11 Page 5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PL685-28.PDF ] | |
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