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PDF PL520-80 Data sheet ( Hoja de datos )
| Número de pieza | PL520-80 | |
| Descripción | Low Phase Noise VCXO | |
| Fabricantes | Micrel | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PL520-80 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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PL520-80
Low Phase Noise VCXO (9.5-65MHz)
FEATURES
19MHz to 65MHz fundamental crystal input.
Output range: 9.5MHz – 65MHz
Complementary outputs: PECL or LVDS output.
Selectable OE Logic (enable high or enable low).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Integrated variable capacitors.
Supports 2.5V or 3.3V Power Supply.
Available in die form.
DESCRIPTION
The PL520-80 is a VCXO IC specifically designed to
work with fundamental crystals between 19MHz and
65MHz. The selectable divide by two feature extends
the operation range from 9.5MHz to 65MHz. It
requires very low current into the crystal resulting in
better overall stability. The OE logic feature allows
selection of enable high or enable low. Furthermore,
it provides selectable CMOS, PECL or LVDS outputs.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Th ic kn e s s
Value
62 x 65 mil
GND
80 m icron x 80 micron
10 mil
BLOCK DIAGRAM
VCON Oscillator
Amplifier
w/
XIN integrated
varicaps
XOUT
OE
Q
Q
S2
PL520-80
DIE CONFIGURATION
65 mil
25 24 23 22 21 20 19 18
XIN 26
XOUT 27
Die ID:
A2020-20C
N/C 28
S2^ 29
OE
30
CTRL
VCON 31
C502A
12345 6 78
(1550,1475)
17 GNDBUF
16 CMOS
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OE_SEL^
Y (0,0)
X
OUTPUT SELECTION AND ENABLE
OUT_SEL1* OUT_SEL0*
(Pad 18)
(Pad 25)
Selected Output*
0 0 High Drive CMOS
0 1 Standard CMOS
1 0 LVDS
1 1 PECL (default)
OE_SELECT OE_CTRL
(Pad 9)
(Pad 30)
State
0
0 Tri-state
1 (Default) Output enabled
1 (Default)
0 (Default) Output enabled
1 Tri-state
Pads #9, #18 & #25: Bond to GND to set to “0”,
No connection results to “default” setting
through internal pull-up.
OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
OUTPUT FREQUENCY SELECTOR
S2
0
1 ( D e f au lt) *
Output
Input/2
Input
*Internally set to ‘Default’ through 60K Ω pull-up resistor
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/11/08 Page 1
1 page  
PL520-80
Low Phase Noise VCXO (9.5-65MHz)
10. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 to (VDD – 2V)
(see figure)
MIN.
VDD – 1.025
MAX.
VDD – 1.620
11. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN. TYP. MAX.
0.6 1.5
0.5 1.5
PECL Levels Test Circuit
OUT
VDD
50 2.0V
PECL Output Skew
OUT
50%
UNITS
V
V
UNITS
ns
ns
OUT
50
OUT
80%
50%
20%
OUT
tR
OUT
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
tF
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/11/08 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PL520-80.PDF ] | |
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