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PDF PL520-30 Data sheet ( Hoja de datos )
| Número de pieza | PL520-30 | |
| Descripción | PECL and LVDS Low Phase Noise VCXO | |
| Fabricantes | Micrel | |
| Logotipo |  |
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PL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FE AT UR E S
65MHz to 130MHz Fundamental Mode Crystals.
Output range (no PLL):
65MHz – 130MHz (3.3V).
65MHz – 105MHz (2.5V).
Low Injection Power for crystal 50uW.
Complementary outputs: PECL or LVDS.
Selectable OE Logic
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DESCRIPTION
The PL520-30 is a VCXO IC specifically designed to
pull frequency fundamental crystals from 65MHz to
130MHz, with selectable PECL or LVDS outputs and
OE logic (enable high or enable low). Its design was
optimized to tolerate higher limits of interelectrodes
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
BLOCK DIAGRAM
VCON Oscillator
Amplifier
w/
XIN integrated
varicaps
XOUT
OE
Q
Q
PL520-30
DIE CONFIGURATION
65 mil
25 24 23 22 21 20 19 18
XIN 26
XOUT 27
Die ID:
A1313-13B
N/C 28
N/C 29
OE
30
CTRL
VCON 31
C502A
12345 6 78
(1550,1475)
17 GNDBUF
16 N/C
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OUTSEL^
Y (0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Th ic kn e s s
Value
62 x 65 mil
GND
80 m icron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
OUTSEL
(Pad #9)
0
1
Selected Output
L VD S
PECL (default)
OESEL
(Pad #25)
0
1 (default)
OE_CTRL
(Pad #30)
0
1
0
1
State
Tr i- s t a te
Output enabled (default)
Output enabled (default)
Tr i- s t a te
Pad #9, #25: Bond to GND to set to “0”. Internal pull up.
Pad #30: Logical states defined by PECL levels if OESEL is “1”
Logical states defined by CMOS levels if OESEL is “0”
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 1
1 page  
PL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
9. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 to (VDD – 2V)
(see figure)
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
VDD – 1.025
VDD – 1.900
MAX.
VDD – 0.750
VDD – 1.620
UNITS
V
V
MIN. TYP. MAX. UNITS
0.6 1.5
0.5 1.5
ns
ns
PECL Levels Test Circuit
OUT
VDD
50 2.0V
PECL Output Skew
OUT
50%
OUT
50
OUT
80%
50%
20%
OUT
tR
OUT
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
tF
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PL520-30.PDF ] | |
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