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IN89C2051 Schematic ( Datenblatt PDF ) - Integral

Teilenummer IN89C2051
Beschreibung 8-BIT MICROCONTROLLER
Hersteller Integral
Logo Integral Logo 

Gesamt 13 Seiten
		
IN89C2051 Datasheet, Funktion
IN89C2051
8-BIT MICROCONTROLLER WITH 2K BYTES FLASH
Description
The IN89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with
2K Bytes of Flash programmable and erasable read only memory (PEROM). The device is
manufactured using Atmel’s high density nonvolatile memory technology and is compatible
with the industry standard MCS-51™ instruction set. By combining a versatile 8-bit CPU
with Flash on a monolithic chip, the Atmel IN89C2051 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control
applications.
The IN89C2051 provides the following standard features: 2K Bytes of Flash, 128
bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and
clock circuitry. In addition, the IN89C2051 is designed with static logic for operation down
to zero frequency and supports two software selectable power saving modes. The Idle
Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt
system to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator disabling all other chip functions until the next hardware reset.
Features
• Compatible with MCS-51™ Products
• 2K Bytes of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-Level Program Memory Lock
• 128 x 8-Bit Internal RAM
• 15 Programmable I/O Lines
• Two 16-Bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial UART Channel
• Direct LED Drive Outputs
• On-Chip Analog Comparator
• Low Power Idle and Power Down Modes
Pin Configuration
1






IN89C2051 Datasheet, Funktion
IN89C2051
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional
branching instructions the same rule above applies. Again, violating the memory
boundaries may cause erratic execution.
For applications involving interrupts the normal interrupt service routine address
locations of the 80C51 family architecture have been preserved.
2. MOVX-related instructions, Data Memory:
The IN89C2051 contains 128 bytes of internal data memory. Thus, in the
IN89C2051 the stack depth is limited to 128 bytes, the amount of available RAM. External
DATA memory access is not supported in this device, nor is external PROGRAM memory
execution. Therefore, no MOVX [...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions, even if they are written in
violation of the restrictions mentioned above. It is the responsibility of the controller user to
know the physical features and limitations of the device being used and adjust the
instructions used correspondingly.
Program Memory Lock Bits
On the chip are two lock bits which can be left unpro-grammed (U) or can be
programmed (P) to obtain the additional features listed in the table below:
Lock Bit Protection Modes(1)
Program Lock Bits
Protection Type
LB1 LB2
1 U U No program lock features.
2 P U Further programming of the Flash is disabled.
3 P P Same as mode 2, also verify is disabled.
Note: 1. The Lock Bits can only be erased with the Chip Erase operation.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain
active. The mode is invoked by software. The content of the on-chip RAM and all the
special functions registers remain unchanged during this mode. The idle mode can be
terminated by any enabled interrupt or by a hardware reset. P1.0 and P1.1 should be set
to ’0’ if no external pullups are used, or set to ’1’ if external pullups are used.
It should be noted that when idle is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles
before the internal reset algorithm takes control. On-chip hardware inhibits access to
internal RAM in this event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write to a port pin when Idle is terminated by reset, the
instruction following the one that invokes Idle should not be one that writes to a port pin or
to external memory.
Power Down Mode
6

6 Page







IN89C2051 pdf, datenblatt
External Clock Drive Waveforms
IN89C2051
External Clock Drive
Symbol
1/tCLCL
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
Parameter
Oscillator Frequency
Clock Period
High Time
Low Time
Rise Time
Fall Time
VCC = 2.7V to 6.0V
Min Max
0 12
83.3
30
30
20
20
VCC = 4.0V to 6.0V Units
Min Max
0 24 MHz
41.6
ns
15 ns
15 ns
20 ns
20 ns
Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 5.0V ± 20%; Load Capacitance = 80 pF)
Symbol
Parameter
12 MHz Osc Variable Oscillator Units
Min Max
Min
Max
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port Clock Cycle Time
1.0 12tCLCL
µs
Output Data Setup to Clock Rising Edge
700
10tCLCL-133
ns
Output Data Hold After Clock Rising Edge 50
2tCLCL-117
ns
Input Data Hold After Clock Rising Edge
0
0
ns
Clock Rising Edge to Input Data Valid
700 10tCLCL-133 ns
Shift Register Mode Timing Waveforms
12

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