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29LV320 Schematic ( PDF Datasheet ) - Eon Silicon Solution
| Teilenummer | 29LV320 |
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| Beschreibung | EN29LV320 | |
| Hersteller | Eon Silicon Solution | |
| Logo |  |
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Gesamt 30 Seiten 
EN29LV320
EN29LV320
32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
• Single power supply operation
- Full voltage range: 2.7 to 3.6 volts read and
write operations
• High performance
- Access times as fast as 70 ns
• Low power consumption (typical values at 5
MHz)
- 9 mA typical active read current
- 20 mA typical program/erase current
- Less than 1 µA current in standby or automatic
sleep mode.
• Flexible Sector Architecture:
- Eight 8-Kbyte sectors, sixty-three 64k-byte
sectors.
- 8-Kbyte sectors for Top or Bottom boot.
- Sector/Sector Group protection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
Additionally, temporary Sector Group
Unprotect allows code changes in previously
locked sectors.
• High performance program/erase speed
- Word program time: 8µs typical
- Sector erase time: 500ms typical
- Chip erase time: 70s typical
• JEDEC Standard compatible
• Standard DATA# polling and toggle bits
feature
• Unlock Bypass Program command supported
• Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
• Support JEDEC Common Flash Interface
(CFI).
• Low Vcc write inhibit < 2.5V
• Minimum 100K program/erase endurance
cycles.
• RESET# hardware reset pin
- Hardware method to reset the device to read
mode.
• WP#/ACC input pin
- Write Protect (WP#) function allows
protection of outermost two boot sectors,
regardless of sector protect status
- Acceleration (ACC) function provides
accelerated program times
• Package Options
- 48-pin TSOP (Type 1)
- 48 ball 6mm x 8mm FBGA
• Commercial and Industrial Temperature
Range.
GENERAL DESCRIPTION
The EN29LV320 is a 32-Megabit, electrically erasable, read/write non-volatile flash memory, organized
as 4,194,304 bytes or 2.097,152 words. Any word can be programmed typically in 8µs. The
EN29LV320 features 3.0V voltage read and write operation, with access times as fast as 70ns to
eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29LV320 has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)
controls, which eliminate bus contention issues. This device is designed to allow either single Sector or
full Chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K
program/erase cycles on each Sector.
.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2005/05/31
 
SA38
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SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
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64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3F1FFF
3F2000–3F3FFF
3F4000–3F5FFF
3F6000–3F7FFF
3F8000–3F9FFF
3FA000–3FBFFF
3FC000–3FDFFF
3FE000–3FFFFF
EN29LV320
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1F8FFF
1F9000–1F9FFF
1FA000–1FAFFF
1FB000–1FBFFF
1FC000–1FCFFF
1FD000–1FDFFF
1FE000–1FEFFF
1FF000–1FFFFF
Note: The address bus is A20:A-1 in byte mode where BYTE# = VILB B or A20:A0 in word mode where
BYTE# = VIHB B
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
6 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2005/05/31
6 Page 
USER MODE DEFINITIONS
Word / Byte Configuration
EN29LV320
The signal set on the BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte
or word configuration. When the BYTE# Pin is set at logic ‘1’, then the device is in word configuration,
DQ15-DQ0 are active and are controlled by CE# and OE#.
On the other hand, if the BYTE# Pin is set at logic ‘0’, then the device is in byte configuration, and only
data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-
stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The
EN29LV320
has
a
CMOS-compatible
standby
mode,
which
reduces
the
current
B
to
<
1µA
(typical).
It
is placed in CMOS-compatible standby when the CE# pin is at VCCB B ± 0.5. RESET# and BYTE# pin must
also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the
maximum
VBCC
current
B
to
<
1mA.
It is placed in TTL-compatible standby when the CE# pin is at V .IHB B
When in standby modes, the outputs are in a high-impedance state independent of the OE# input.
Automatic Sleep Mode
The EN29LV320 has a automatic sleep mode, which minimizes power consumption. The devices will
enter this mode automatically when the states of address bus remain stable for tacc + 30ns. ICC4 in the DC
Characteristics table shows the current specification. With standard access times, the device will output
new data when addresses change.
Read Mode
The device is automatically set to reading array data after device power-up or hardware reset. No
commands are required to retrieve data. The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm
After the device accepts an Sector Erase Suspend command, the device enters the Sector Erase
Suspend mode. The system can read array data using the standard read timings, except that if it reads at
an address within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Sector Erase Suspend mode, the system may once again read array data
with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional
information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high
or while in the autoselect mode. See the “Reset Command” for additional details.
Output Disable Mode
When the OE# pin is at a logic high level (V )IHB B , the output from the EN29LV320 is disabled. The output
pins are placed in a high impedance state.
Autoselect Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VIDB B (10.5 V to 11.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
12 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2005/05/31
12 Page | ||
| Seiten | Gesamt 30 Seiten | |
| PDF Download | [ 29LV320 Schematic.PDF ] | |
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