KSZ8081RNB Schematic ( PDF Datasheet ) - Micrel Semiconductor

Teilenummer	KSZ8081RNB
Beschreibung	10Base-T/100Base-TX Physical Layer Transceiver
Hersteller	Micrel Semiconductor
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Gesamt 30 Seiten KSZ8081MNX/KSZ8081RNB 10Base-T/100Base-TX Physical Layer Transceiver Revision 1.4 General Description The KSZ8081 is a single-supply 10Base-T/100Base-TX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ8081 is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core. The KSZ8081MNX offers the Media Independent Interface (MII) and the KSZ8081RNB offers the Reduced Media Independent Interface (RMII) for direct connection with MII/RMII-compliant Ethernet MAC processors and switches. A 25MHz crystal is used to generate all required clocks, including the 50MHz RMII reference clock output for the KSZ8081RNB. The KSZ8081 provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ8081 I/Os and the board. Micrel LinkMD® TDR-based cable diagnostics identify faulty copper cabling. The KSZ8081MNX and KSZ8081RNB are available in 32- pin, lead-free QFN packages (see “Ordering Information”). Datasheets and support documentation are available on website at: www.micrel.com. Features • Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver • MII interface support (KSZ8081MNX) • RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8081RNB) • Back-to-back mode support for a 100Mbps copper repeater • MDC/MDIO management interface for PHY register configuration • Programmable interrupt output • LED outputs for link, activity, and speed status indication • On-chip termination resistors for the differential pairs • Baseline wander correction • HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option • Auto-negotiation to automatically select the highest link- up speed (10/100Mbps) and duplex (half/full) • Power-down and power-saving modes • LinkMD TDR-based cable diagnostics to identify faulty copper cabling • Parametric NAND Tree support for fault detection between chip I/Os and the board • HBM ESD rating (6kV) Functional Diagram LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com August 19, 2015 Revision 1.4 Micrel, Inc. KSZ8081MNX/KSZ8081RNB List of Figures Figure 1. Auto-Negotiation Flow Chart.................................................................................................................................. 21 Figure 2. KSZ8081MNX MII Interface ................................................................................................................................... 24 Figure 3. KSZ8081RNB RMII Interface (25MHz Clock Mode).............................................................................................. 27 Figure 4. KSZ8081RNB RMII Interface (50MHz Clock Mode).............................................................................................. 27 Figure 5. KSZ8081MNX/RNB to KSZ8081MNX/RNB Back-to-Back Copper Repeater ....................................................... 28 Figure 6. Typical Straight Cable Connection ........................................................................................................................ 31 Figure 7. Typical Crossover Cable Connection .................................................................................................................... 31 Figure 8. Local (Digital) Loopback ........................................................................................................................................ 32 Figure 9. Remote (Analog) Loopback ................................................................................................................................... 33 Figure 10. KSZ8081MNX/RNB Power and Ground Connections......................................................................................... 38 Figure 11. MII SQE Timing (10Base-T) ................................................................................................................................ 54 Figure 12. MII Transmit Timing (10Base-T) .......................................................................................................................... 55 Figure 13. MII Receive Timing (10Base-T) ........................................................................................................................... 56 Figure 14. MII Transmit Timing (100Base-TX)...................................................................................................................... 57 Figure 15. MII Receive Timing (100Base-TX)....................................................................................................................... 58 Figure 16. RMII Timing – Data Received from RMII ............................................................................................................. 59 Figure 17. RMII Timing – Data Input to RMII ........................................................................................................................ 59 Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 60 Figure 19. MDC/MDIO Timing............................................................................................................................................... 61 Figure 20. Power-up/Reset Timing ....................................................................................................................................... 62 Figure 21. Recommended Reset Circuit............................................................................................................................... 63 Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ...................................................... 63 Figure 23. Reference Circuits for LED Strapping Pins ......................................................................................................... 64 Figure 24. 25MHz Crystal/Oscillator Reference Clock Connection ...................................................................................... 65 Figure 25. 50MHz Oscillator Reference Clock Connection .................................................................................................. 65 Figure 26. Typical Magnetic Interface Circuit........................................................................................................................ 66 August 19, 2015 6 Revision 1.4 6 Page Micrel, Inc. KSZ8081MNX/KSZ8081RNB Strapping Options – KSZ8081MNX The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly. Pin Number Pin Name 15 PHYAD2 14 PHYAD1 13 PHYAD0 Type(5) Ipd/O Ipd/O Ipu/O Pin Function PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0 to 7 with PHY Address 1 as the default value. PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to Register 16h, Bit [9]. PHY Address bits [4:3] are set to 00 by default. The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset: 18 CONFIG2 Ipd/O CONFIG[2:0] 29 CONFIG1 Ipd/O 000 28 CONFIG0 Ipd/O 110 Mode MII (default) MII back-to-back 001 – 101, 111 Reserved – not used Isolate Mode: 20 ISO Ipd/O Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10]. Speed Mode: Pull-up (default) = 100Mbps 31 SPEED Ipu/O Pull-down = 10Mbps At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as the speed select, and also is latched into Register 4h (auto-negotiation advertisement) as the speed capability support. Duplex Mode: 16 DUPLEX Ipu/O Pull-up (default) = Half-duplex Pull-down = Full-duplex At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8]. Note: 5. Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). August 19, 2015 12 Revision 1.4 12 Page
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