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Número de pieza | HY57V561620FLTP-5 | |
Descripción | 256M (16M x 16bit) Hynix SDRAM Memory | |
Fabricantes | Hynix Semiconductor | |
Logotipo | ||
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No Preview Available ! 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
256M (16Mx16bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 4,194,304 x 16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Dec. 2009
1
1 page 111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
256Mb Synchronous DRAM(16M x 16) FEATURES
● Standard SDRAM Protocol
● Internal 4bank operation
● Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V
● All device pins are compatible with LVTTL interface
● Low Voltage interface to reduce I/O power
● 8,192 Refresh cycles / 64ms
● Programmable CAS latency of 2 or 3
● Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
● 0oC ~ 70oC Operation
● Package Type : 54_Pin TSOPII (Lead Free, Lead)
HY57V561620F(L)TP Series : Lead Free
HY57V561620F(L)T Series : Leaded
ORDERING INFORMATION
Part Number
HY57V561620FT-6
HY57V561620FT-H
HY57V561620FT-5
HY57V561620FLT-6
HY57V561620FLT-H
HY57V561620FLT-5
HY57V561620FTP-6
HY57V561620FTP-H
HY57V561620FTP-5
HY57V561620FLTP-6
HY57V561620FLTP-H
HY57V561620FLTP-5
Clock
Frequency
166MHz
133MHz
200MHz
166MHz
133MHz
200MHz
166MHz
133MHz
200MHz
166MHz
133MHz
200MHz
CAS
Latency
3
3
3
3
3
3
3
3
3
3
3
3
Power
Normal
Low
Power
Normal
Low
Power
Voltage
Organization
Interface
54Pin
TSOP
Leaded
3.3V
4Banks x 4Mbits
x16
LVTTL
Lead
Free
Note:
1. HY57V561620FT(P) Series: Normal power
2. HY57V561620FLT(P) Series: Low Power
3. HY57V561620F(L)T Series: Leaded 54Pin TSOPII
4. HY57V561620F(L)TP Series: Lead Free 54Pin
Rev 1.2 / Dec. 2009
5
5 Page 111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
DC CHARACTERISTICS II (TA= 0 to 70oC)
Parameter
Operating
Current
Precharge
Standby
Current
in Power Down
Mode
Precharge
Standby
Current
in Non Power
Down Mode
Active Standby
Current in
Power Down
Mode
Active Standby
Current in Non
Power Down
Mode
Burst Mode Op-
erating Current
Auto Refresh
Current
Self Refresh
Current
Symbol
IDD1
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4
IDD5
IDD6
Test Condition
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
tCK ≥ tCK(min), IOL=0mA
All banks active
tRC ≥ tRC(min), All banks active
CKE ≤ 0.2V
Normal
Low Power
Speed
56H
110 100 90
1.0
1.0
15
8
3
3
30
20
110 100 90
190 180 170
2.0
1.0
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
1
1
2
3
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY57V561620FT(P) Series: Normal, HY57V561620FLT(P) Series: Low Power
Rev 1.2 / Dec. 2009
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet HY57V561620FLTP-5.PDF ] |
Número de pieza | Descripción | Fabricantes |
HY57V561620FLTP-5 | 256M (16M x 16bit) Hynix SDRAM Memory | Hynix Semiconductor |
HY57V561620FLTP-6 | 256M (16M x 16bit) Hynix SDRAM Memory | Hynix Semiconductor |
HY57V561620FLTP-H | 256M (16M x 16bit) Hynix SDRAM Memory | Hynix Semiconductor |
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