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HY57V561620FTP-6 Schematic ( PDF Datasheet ) - Hynix Semiconductor
| Teilenummer | HY57V561620FTP-6 |
|
| Beschreibung | 256M (16M x 16bit) Hynix SDRAM Memory | |
| Hersteller | Hynix Semiconductor | |
| Logo |  |
|
Gesamt 30 Seiten 
256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
256M (16Mx16bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 4,194,304 x 16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Dec. 2009
1
 
54 TSOP II Pin ASSIGNMENTS
111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 Pin TSOPII
400mil x 875mil
0.8mm pin pitch
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC
39 UDQM
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Rev 1.2 / Dec. 2009
6
6 Page 
111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System Clock Cycle Time
CL = 3
CL = 2
Clock High Pulse Width
Clock Low Pulse Width
Access Time From Clock
CL = 3
CL = 2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in CL = 3
High-Z Time
CL = 2
Symbol
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
5
Min Max
5.0
1000
10
2.0 -
2.0 -
- 4.5
- 6.0
2.0 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.0 -
- 4.5
- 6.0
6
Min Max
6.0 1000
7.5 1000
2.5 -
2.5 -
- 5.4
-6
2.0 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.0 -
2.7 5.4
2.7 5.4
H
Min Max
7.5 1000
10 1000
2.5 -
2.5 -
- 5.4
-6
2.5 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.0 -
2.7 5.4
36
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
2
2
1
1
1
1
1
1
1
1
Note:
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added
to the parameter.
Rev 1.2 / Dec. 2009
12
12 Page | ||
| Seiten | Gesamt 30 Seiten | |
| PDF Download | [ HY57V561620FTP-6 Schematic.PDF ] | |
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