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PDF ADP5074 Data sheet ( Hoja de datos )
| Número de pieza | ADP5074 | |
| Descripción | DC-to-DC Inverting Regulator | |
| Fabricantes | Analog Devices | |
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Data Sheet
2.4 A, DC-to-DC Inverting Regulator
ADP5074
FEATURES
Wide input voltage range: 2.85 V to 15 V
Adjustable negative output to VIN − 39 V
Integrated 2.4 A main switch
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Precision enable control
Power-good output
UVLO, OCP, OVP, and TSD protection
3 mm × 3 mm, 16-lead LFCSP
−40°C to +125°C junction temperature
Supported by the ADIsimPower tool set
APPLICATIONS
Bipolar amplifiers, ADCs, digital-to-analog converters
(DACs), and multiplexers
High speed converters
Radio frequency (RF) power amplifier (PA) bias
Optical modules
GENERAL DESCRIPTION
The ADP5074 is a high performance dc-to-dc inverting regulator
used to generate negative supply rails.
The input voltage range of 2.85 V to 15 V supports a wide variety of
applications. The integrated main switch enables the generation of
an adjustable negative output voltage down to 39 V below the
input voltage.
The ADP5074 operates at a pin selected 1.2 MHz/2.4 MHz
switching frequency. The ADP5074 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. The regulator implements
programmable slew rate control circuitry for the MOSFET
driver stage to reduce electromagnetic interference (EMI).
The ADP5074 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up. During
shutdown, the regulator completely disconnects the load from the
input supply to provide a true shutdown. A power good pin is
available to indicate the output is stable.
TYPICAL APPLICATION CIRCUIT
VIN
CIN
ON
OFF
CVREG
AVIN
PVIN
VREF
ADP5074 FB
EN
VREG
SW
SS
PWRGD
PWRGD
SLEW
CVREF
RFB
RFT
D1
L1
VOUT
COUT
COMP SYNC/FREQ
CC RC
GND
Figure 1.
Other key safety features in the ADP5074 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The ADP5074 is available in a 16-lead LFCSP and is rated for a
−40°C to +125°C operating junction temperature range.
Table 1. Related Devices
Device
Boost
Inverter
Switch (A) Switch (A)
ADP5070 1.0
0.6
ADP5071 2.0
1.2
ADP5073
ADP5074
ADP5075
Not
applicable
Not
applicable
Not
applicable
1.2
2.4
0.8
Package
20-lead LFCSP (4 mm ×
4 mm) and TSSOP
20-lead LFCSP (4 mm ×
4 mm) and TSSOP
16-lead LFCSP (3 mm ×
3 mm)
16-lead LFCSP (3 mm ×
3 mm)
12-ball WLCSP
(1.61 mm × 2.18 mm)
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
PVIN, AVIN
SW
GND
VREG
EN, FB, SYNC/FREQ, PWRGD
COMP, SLEW, SS, VREF
Operating Junction
Temperature Range
Storage Temperature
Range
Soldering Conditions
Rating
−0.3 V to +18 V
PVIN − 40 V to PVIN + 0.3 V
−0.3 V to +0.3 V
−0.3 V to lower of AVIN + 0.3 V or +6 V
−0.3 V to +6 V
−0.3 V to VREG + 0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ADP5074
THERMAL RESISTANCE
θJA and ΨJT are based on a 4-layer printed circuit board (PCB)
(two signals and two power planes) with thermal vias connecting
the exposed pad to a ground plane as recommended in the
Layout Considerations section. θJC is measured at the top of the
package and is independent of the PCB. The ΨJT value is more
appropriate for calculating junction to case temperature in the
application.
Table 4. Thermal Resistance
Package Type
θJA
16-Lead LFCSP
75.01
θJC ΨJT
55.79 0.95
Unit
°C/W
ESD CAUTION
Rev. 0 | Page 5 of 17
5 Page 
Data Sheet
PRECISION ENABLING
The ADP5074 has an enable pin that features a precision enable
circuit with an accurate reference voltage. This reference allows the
ADP5074 to be sequenced easily from other supplies. It can also
be used as a programmable UVLO input by using a resistor divider.
The enable pin has an internal pull-down resistor that defaults
to off when the pin is floating. When the voltage at the enable pin is
greater than the VTH_H reference level, the regulator is enabled.
SOFT START
The regulator in the ADP5074 includes soft start circuitry that
ramps the output voltage in a controlled manner during startup,
thereby limiting the inrush current. The soft start time is internally
set to the fastest rate when the SS pin is open.
Connecting a resistor between SS and ground allows the
adjustment of the soft start delay.
SLEW RATE CONTROL
The ADP5074 uses programmable output driver slew rate
control circuitry. This circuitry reduces the slew rate of the
switching node as shown in Figure 22, resulting in reduced
ringing and lower EMI. To program the slew rate, connect the
SLEW pin to the VREG pin for normal mode, to the GND pin
for slow mode, or leave it open for fast mode. This logic allows the
use of an open-drain output from a noise sensitive device to
switch the slew rate from fast to slow, for example, during
analog-to-digital converter (ADC) sampling.
Note that slew rate control causes a trade-off between efficiency
and low EMI.
FASTEST
SLOWEST
Figure 22. Switching Node at Various Slew Rate Settings
CURRENT-LIMIT PROTECTION
The inverting regulator in the ADP5074 includes current-limit
protection circuitry to limit the amount of forward current
allowed through the MOSFET switch.
ADP5074
When the peak inductor current exceeds the current-limit
threshold, the power MOSFET switch is turned off for the
remainder of that switch cycle. If the peak inductor current
continues to exceed the overcurrent limit, the regulator enters
hiccup mode. The regulator stops switching and then restarts
with a new soft start cycle after tHICCUP and repeats until the
overcurrent condition is removed.
OVERVOLTAGE PROTECTION
An overvoltage protection mechanism is present on the FB pin
for the inverting regulator.
When the voltage on the FB pin drops below the VOV threshold,
the switching stops until the voltage rises above the threshold.
This functionality is enabled after the soft start period has elapsed.
POWER GOOD
The ADP5074 provides an open-drain power-good output to
indicate when the output voltage reaches a target level.
A pull-up voltage must be provided on the PWRGD pin through
an external resistor to provide a high output when the power is
good. The pull-up voltage is typically sourced from the VREG pin
although an external supply may be used with a maximum voltage
of VDS_PG .(MAX) The power-good FET pulls down when the supply
on the PVIN pin rises above VPG(SUPPLY) and the FET remains on
until the enable is brought high and soft start has completed. Note
that if an external supply is used, the power-good output may be
high until PVIN reaches VDS_PG .(MAX)
As soon as the device is enabled and soft start is complete, the
power-good function monitors the voltage on the FB pin. If the
voltage VREF − VFB is greater than the VPG (GOOD) threshold, the
power-good FET turns off, allowing the power-good output to
be pulled up to VREG or an external supply signaling a power-
good valid condition. If the voltage VREF − VFB is less than the
VPG (BAD) threshold, the power-good FET turns on, pulling the
output to GND, indicating the power output is not good.
THERMAL SHUTDOWN
In the event that the ADP5074 junction temperature rises above
TSHDN, the thermal shutdown circuit turns off the IC. Extreme
junction temperatures can be the result of prolonged high current
operation, poor circuit board design, and/or high ambient
temperature. Hysteresis is included so that when thermal shutdown
occurs, the ADP5074 does not return to operation until the on-
chip temperature drops below TSHDN − THYS. When resuming from
thermal shutdown, a soft start is performed.
Rev. 0 | Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADP5074.PDF ] | |
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